View STANDARDMICROSYSTEMSCORP-EMC2103-3-KP_6659492.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

smsc emc2103 datasheet revision 0.85 (01-29-08) datasheet product features emc2103 rpm-based fan controller with hw thermal shutdown the emc2103 is an smbus co mpliant fan controller with up to up to 3 external and 1 internal temperature channels. the fan driver can be operated using two methods each with two modes. the methods include an rpm based fan speed control algorithm and a direct pwm drive setting. the modes include manually programming the desired sett ings or using the internal programmable temperature look-up table to select the desired setting based on measured temperature. the temperature monitors offer 1c accuracy (for external diodes) with sophisticated features to reduce errors introduced by series resistance and beta variation of substrate thermal diode transistors commonly found in processors. the emc2103 also includes a hardware programmable temperature limit and dedicated system shutdown output for thermal protection of critical circuitry. applications ? notebook computers ? projectors ? graphics cards ? industrial and networking equipment features ? programmable fan control circuit ? 4-wire fan compatible ? high and low frequency pwm ? rpm based fan control algorithm ? 2.5% accuracy from 500rpm to 16k rpm ? detects fan aging and variation ? temperature look-up table ? allows programmed fan response to temperature ? controls fan speed or pwm drive setting ? allows externally set temperature data to drive fan ? supports dts data from cpu ? up to three external temperature channels (emc2103-2 only) ? supports 45nm, 60nm, and 90nm cpu diodes ? automatically detects and s upports cpus requiring bjt or transistor models ? resistance error correction ? supports discrete transistors (i.e. 2n3904) ? 1c accurate (60c to 125c) ? 0.125c resolution ? hardware programmable thermal shutdown temperature ? cannot be altered by software ? 65c to 127c range ? programmable high and low limits for all channels ? internal temperature monitor ? 2c accuracy ? 0.125c resolution ? 3.3v supply voltage ? smbus 2.0 compliant ? smbus alert compatible ? two dedicated gpios (emc2103-2 and emc2103-4 only) ? available in 12-pin, qfn lead-free rohs compliant package (emc2103-1 and emc2103-3) or 16-pin, qfn lead-free rohs compliant package (emc2103-2 and emc2103-4)
order numbers: ordering number package features emc2103-1-kp 12 pin, qfn lead-free, rohs compliant one external diode, rpm based fan speed control algorithm, high frequency pwm driver, hw thermal / critical shutdown, eeprom load disabled emc2103-2-ap 16 pin, qfn lead-free, rohs compliant up to three external diodes, rpm based fan speed control algorithm, high frequency pwm driver, hw thermal / critical shutdown, 2 gpios, eeprom load disabled emc2103-3-kp 12 pin, qfn lead-free, rohs compliant one external diode, rpm based fan speed control algorithm, high frequency pwm driver, hw thermal / critical shutdown, eeprom load enabled emc2103-4-ap 16 pin, qfn lead-free, rohs compliant up to three external diodes, rpm based fan speed control algorithm, high frequency pwm driver, hw thermal / critical shutdown, 2 gpios, eeprom load enabled rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 2 smsc emc2103 datasheet 80 arkay drive, hauppauge, ny 11788 (631) 435-6000, fax (631) 273-3123 copyright ? 2008 smsc or its subsidiaries. all rights reserved. circuit diagrams and other information relating to smsc produc ts are included as a means of illustrating typical applications. consequently, complete information sufficient for construction purposes is not necessarily given. although the information has been checked and is believed to be accurate, no re sponsibility is assumed for inaccuracies. smsc reserves the right to make changes to specifications and produc t descriptions at any time without notice. contact your local sm sc sales office to obtain the latest specifications before placing your product order. the provision of this inform ation does not convey to the purchaser of the described semicond uctor devices any licenses under any patent rights or other intellectual property rights of smsc or others. all sales are expressly conditional on your agreement to the te rms and conditions of the most recently dated version of smsc's standard terms of sale agreement dated before the date of your order (the "terms of sale agreement"). the pro duct may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. anomaly sheets are availab le upon request. smsc products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. any and all such uses without prior written approval of an officer of smsc and further testing and/or modification will be fully at the risk of the customer. copies of this document or other smsc literature, as well as the terms of sale agreement, may be obtained by visiting smsc?s website at h ttp://www.smsc.com. smsc is a registered trademark of standard microsystems corporat ion (?smsc?). product names and company na mes are the trademarks of their respective holders. smsc disclaims and excludes any and all warrant ies, including without limi tation any and all implied warranties of merchantabil ity, fitness for a particular purpose, title, a nd against infringement and the like, and any and all warranties arising from any cou rse of dealing or usage of trade. in no event shall smsc be liable for any direct, incidental, indi rect, special, punitive, or cons equential damages; or for lost data, profits, savings or revenues of any kind; regardless of the form of action, whether based on contrac t; tort; negligence of smsc or others; strict liability; breach of wa rranty; or otherwise; whether or not any remedy of buyer is h eld to have failed of its essential purpose, and whether or not smsc has been advised of the possibility of such damages.
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 3 revision 0.85 (01-29-08) datasheet table of contents chapter 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 chapter 2 pin layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 chapter 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 smbus electrical specifications (client mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 chapter 4 communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 system management bus interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 write byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3 read byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.4 send byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.5 receive byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.6 alert response address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.7 smbus address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.8 smbus time-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 chapter 5 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1 critical/thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1.1 shdn_sel pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1.2 trip_set pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2 fan control modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3 pwm fan driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.4 fan control look-up table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.4.1 programming the look up table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.4.2 dts support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.5 rpm based fan speed control algorithm (fsc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.5.1 programming the rpm based fan speed control algo rithm . . . . . . . . . . . . . . . . . . . . . 28 5.6 tachometer measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.6.1 stalled fan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.6.2 aging fan or invalid drive detectio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.7 spin up routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.8 ramp rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.9 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.10 fault queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.11 temperature monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.11.1 dynamic averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.11.2 resistance error correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 5.11.3 beta compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.11.4 digital averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.12 diode connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.12.1 diode faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.13 gpios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 chapter 6 register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1.1 lock entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.2 temperature data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.3 critical/thermal shutdown temperature register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.4 pushed temperature registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 4 smsc emc2103 datasheet 6.5 trip_set voltage register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.6 ideality factor registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.7 beta configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.8 rec configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.9 critical temperature limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.10 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.11 configuration 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.12 interrupt status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.13 error status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.13.1 tcrit status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.14 fan status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.15 interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.16 fan interrupt enable register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.17 pwm configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.18 pwm base frequency register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.19 limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.20 fan setting registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.21 pwm divide register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.22 fan configuration 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.23 fan configuration 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.24 gain register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.25 fan spin up configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.26 fan step register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.27 fan minimum drive register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.28 valid tach count register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.29 fan drive fail band registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.30 tach target register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.31 tach reading register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.32 look up table configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.33 look up table registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.34 gpio direction register (emc2103-2 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.35 gpio output configuration register (emc2103-2 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.36 gpio input register (emc2103-2 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.37 gpio output register (emc2103-2 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.38 gpio interrupt enable register (emc210 3-2 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.39 gpio status register (emc2103-2 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.40 software lock register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.41 product features register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.42 product id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.43 manufacturer id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.44 revision register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 chapter 7 package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.1 emc2103-1 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.2 emc2103-2 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 appendix a look up table operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 a.1 example #1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 a.2 example #2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 appendix b rpm to tachometer count look up tables . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 b.1 1k rpm range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 5 revision 0.85 (01-29-08) datasheet list of figures figure 1.1 emc2103 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2.1 emc2103-1 pin diagram (12 pin qfn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2.2 emc2103-2 pin diagram (16 pin qfn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4.1 smbus timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 5.1 system diagram for emc2103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 5.2 block diagram of critical / thermal shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 5.3 fan control look-up table example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 5.4 rpm based fan speed control algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 5.5 spin up routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 5.6 ramp rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 5.7 diode connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 7.1 preliminary 12 pin qfn 4mm x 4mm package dimensio ns . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 7.2 preliminary 12 pin qfn 4mm x 4mm package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 7.3 recommended pcb footprint 12-pin qfn 4mm x 4mm. . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 7.4 preliminary 16 pin qfn 4mm x 4mm package dimension s . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 7.5 preliminary 16 pin qfn 4mm x 4mm package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 7.6 recommended pcb footprint 16-pin qfn 4mm x 4mm. . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 6 smsc emc2103 datasheet list of tables table 2.1 pin description for emc2103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 2.2 pin types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3.2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3.3 smbus electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4.1 protocol format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 4.2 write byte protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 4.3 read byte protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4.4 send byte protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4.5 receive byte protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4.6 alert response address protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5.1 shdn_sel pin decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 5.2 trip_set resistor setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 5.3 fan controls active for operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 5.4 dynamic averaging behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 6.1 emc2103 register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 6.2 temperature data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 6.3 temperature data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 6.4 critical/thermal shutdown temperature register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 6.5 critical / thermal shutdown data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 6.6 pushed temperature register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 6.7 trip_set voltage register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 6.8 ideality factor registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 6.9 ideality factor look-up table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 6.10 beta configuration register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 6.11 beta compensation look up table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 6.12 rec configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 6.13 limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 6.14 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 6.15 configuration 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 6.16 fault queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 6.17 conversion rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 6.18 interrupt status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 6.19 error status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 6.20 fan status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 6.21 interrupt enable register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 6.22 fan interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 6.23 pwm configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 6.24 pwm base frequency register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 6.25 pwm_basex[1:0] it decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 6.26 limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 6.27 fan driver setting register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 6.28 pwm divide register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 6.29 fan configuration 1 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 6.30 range decode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 6.31 minimum edges for fan ro tation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 6.32 update time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 6.33 fan configuration 2 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 6.34 derivative options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 6.35 error range options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 6.36 gain register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 6.37 gain decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 7 revision 0.85 (01-29-08) datasheet table 6.38 fan spin up configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 6.39 drive_fail_cnt[1:0] bit decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 6.40 spin level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 6.41 spin time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 6.42 fan step register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 6.43 minimum fan drive register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 6.44 valid tach count register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 6.45 fan drive fail band registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 6.46 tach target register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 6.47 tach reading register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 6.48 look up table configuration register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 6.49 look up table registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 6.50 gpio direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 6.51 gpio output configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 6.52 gpio input register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 6.53 gpio output register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 6.54 gpio interrupt enable register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 6.55 gpio status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 6.56 software lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 6.57 product features register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 6.58 shdn_sel[2:0] encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 6.59 product id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 6.60 manufacturer id register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 6.61 revision register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table a.1 look up table format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table a.2 look up table example #1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 table a.3 fan speed control table example #1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table a.4 fan speed determination for example #1 (using settings in ta b l e a . 3 ) . . . . . . . . . . . . . . . . . 77 table a.5 look up table example #2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8 table a.6 fan speed control table example #2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table a.7 fan speed determination for example #2 (using settings in ta b l e a . 6 ) . . . . . . . . . . . . . . . . . 79 table b.1 tachometer count to rpm look up table (range = 1000 rpm). . . . . . . . . . . . . . . . . . . . . . 80
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 8 smsc emc2103 datasheet chapter 1 block diagram figure 1.1 emc2103 block diagram analog mux external temp diodes internal temp diode 11 bit adc temp registers smbus slave protocol configuration dp1 dn1 smclk smdata temp limit registers thermal shutdown logic tach tach lookup table / rpm control vdd gnd pwm driver pwm dp2 / dn3* dn2 / dp3* * denote emc2103-2 pins only sys_shdn alert shdn_sel trip_set gpio gpio1* gpio2*
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 9 revision 0.85 (01-29-08) datasheet chapter 2 pin layout figure 2.1 emc2103-1 pin diagram (12 pin qfn) emc2103-1 12-qfn 1 2 3 4 5 6 9 8 7 12 11 10 dn dp vdd smclk smdata tach gnd pwm alert sys_shdn shdn_sel trip_set
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 10 smsc emc2103 datasheet figure 2.2 emc2103-2 pin diagram (16 pin qfn) table 2.1 pin description for emc2103 pin number emc2103-1 pin number emc2103 -2 pin name pin function pin type 11dn1 negative (cathode) analog input for external diode 1. aio 22dp1 positive (anode) analog input for external diode 1. aio 3 3 vdd power supply power n/a 4 gpio1 gpi1 - general purpose input (default) di (5v) gpo1 - open drain digital output od (5v) gpo1 - push-pull digital output do emc2103-2 16-qfn 2 3 4 5 6 7 12 11 10 dn1 dp1 vdd smclk smdata tach gnd pwm alert sys_shdn shdn_sel trip_set 8 9 1 16 15 14 13 dn2 / dp3 dp2 / dn3 gpio1 gpio2
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 11 revision 0.85 (01-29-08) datasheet the pin type are described in detail below. a ll pins labelled with (5v) are 5v tolerant. n/a 5 gpio2 gpi2 - general purpose input (default) di (5v) gpo2 - open drain digital output od (5v) gpo2 - push-pull digital output do 4 6 alert active low interrupt - requires external pull-up resistor. od (5v) 5 7 sys_shdn active low critical / thermal shutdown output - requires external pull-up resistor od (5v) 68smdata smbus data input/output - requires external pull-up resistor diod (5v) 79smclk smbus clock input - requires external pull-up resistor di (5v) 8 10 tach tachometer input for the fan di (5v) 911pwm pwm - open drain pwm drive output for the fan (default) od (5v) pwm - push-pull pwm drive output for the fan do 10 12 gnd ground connection power 11 13 shdn_sel selects the hardware shutdown channel and operating mode aio 12 14 trip_set voltage input to set the critical / thermal shutdown threshold aio n/a 15 dn2 / dp3 negative (cathode) analog input for external diode 2 and positive (anode) analog input for external diode 3 aio n/a 16 dp2 / dn3 positive (anode) analog input for external diode 2 and negative (cathode) connection for external diode 3 aio table 2.1 pin description for emc2103 (continued) pin number emc2103-1 pin number emc2103 -2 pin name pin function pin type
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 12 smsc emc2103 datasheet table 2.2 pin types pin type description power this pin is used to supply power or ground to the device. di digital input - this pin is used as a digital input. this pin is 5v tolerant. aio analog input / output - this pin is used as an i/o for analog signals. do push / pull digital output - this pin is used as a digital output. it can both source and sink current. diod digital input / open drain output this pin is used as an digital i/o. when it is used as an output, it is open drain and requires a pull-up resistor. this pin is 5v tolerant. od open drain digital output - this pin is used as a digital output. it is open drain and requires a pull-up resistor. this pin is 5v tolerant.
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 13 revision 0.85 (01-29-08) datasheet chapter 3 electrical characteristics note: stresses above those listed could cause permane nt damage to the device. this is a stress rating only and functional operation of the devic e at any other condition above those indicated in the operation sections of this specification is not implied. when powering this device from laboratory or system power supplie s, it is important that the absolute maximum ratings not be exceeded or device failure can result. some po wer supplies exhibit voltage spikes on their outputs when the ac power is switched on or off. in addition, voltage transients on the ac power line may appear on the dc output. if this po ssibility exists, it is suggested that a clamp circuit be used. note: all voltages are relative to ground. note: ja numbers are based on a recommended four 12 mil vias connecting the thermal pad to pcb ground. table 3.1 absolute maximum ratings voltage on 5v tolerant pins -0.3 to 5.5 v voltage on vdd pin -0.3 to 4 v voltage on any other pin to gnd -0.3 to v dd + 0.3 v package power dissipation 0.8w up to t a = 85c w junction to ambient ( ja ) 50 c/w operating ambient temperature range -40 to 125 c storage temperature range -55 to 150 c esd rating, all pins, hbm 2000 v
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 14 smsc emc2103 datasheet 3.1 electrical specifications table 3.2 electrical specifications vdd = 3v to 3.6v, t a = -40c to 125c, all typical values at t a = 27c unless otherwise noted. characteristic symbol min typ max unit conditions dc power supply voltage v dd 33.33.6v supply current i dd 1.3 1.8 ma 4 conversions / second, fan driver active at maximum pwm frequency, dynamic averaging enabled (emc2103-2) 11.5ma 4 conversions / second, fan driver active at maximum pwm frequency, dynamic averaging enabled (emc2103-1) 450 750 ua 1 conversions / second, fan driver not active, dynamic averaging disabled first conversion ready t conv_t 300 ms time after power up before all channels updated smbus delay t smb_d 10 ms time before smbus communications should be sent by host external temperature monitors temperature accuracy 0.5 1 c 60c < t diode < 125c 30c < t a < 100c 1 2 c -40c < t diode < 125c temperature resolution 0.125 c diode decoupling capacitor c filter 2200 2700 pf connected across external diode, cpu, gpu, or amd diode resistance error corrected r series 100 ohm sum of series resistance in both dp and dn lines internal temperature monitor temperature accuracy t die 1 2 c temperature resolution 0.125 c pwm fan driver pwm resolution pwm 256 steps pwm duty cycle duty 0 100 % trip_set measurement voltage accuracy v trip 0.5 1 %
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 15 revision 0.85 (01-29-08) datasheet 3.2 smbus electrical spec ifications (client mode) temperature decode accuracy t trip 0.5 c 1% external resistor 1 2 c 5% external resistor rpm based fan controller tachometer range tach 480 16000 rpm tachometer setting accuracy tach 2.5 5 % digital i/o pins input high voltage v ih 2.0 v input low voltage v il 0.8 v output high voltage v oh vdd - 0.4 v 8 ma current drive output low voltage v ol 0.4 v 8 ma current sink leakage current i leak 5 ua alert and sys_shdn pins device powered or unpowered t a < 85c table 3.3 smbus electrical specifications vdd= 3v to 3.6v, t a = -40c to 125c typical values are at t a = 27c unless otherwise noted. characteristic symbol min typ max units conditions smbus interface input high/low current i ih / i il 5 ua device powered or unpowered t a < 85c input capacitance c in 410 pf smbus timing clock frequency f smb 10 400 khz spike suppression t sp 50 ns bus free time start to stop t buf 1.3 us setup time: start t su:sta 0.6 us setup time: stop t su:stp 0.6 us data hold time t hd:dat 0.6 6 us data setup time t su:dat 0.6 72 us table 3.2 electrical specifications (continued) vdd = 3v to 3.6v, t a = -40c to 125c, all typical values at t a = 27c unless otherwise noted. characteristic symbol min typ max unit conditions
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 16 smsc emc2103 datasheet clock low period t low 1.3 us clock high period t high 0.6 us clock/data fall time t fall 300 ns min = 20+0.1c load ns clock/data rise time t rise 300 ns min = 20+0.1c load ns capacitive load c load 400 pf total per bus line table 3.3 smbus electrical specifications (continued) vdd= 3v to 3.6v, t a = -40c to 125c typical values are at t a = 27c unless otherwise noted. characteristic symbol min typ max units conditions
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 17 revision 0.85 (01-29-08) datasheet chapter 4 communications 4.1 system management bus interface protocol the emc2103 communicates with a host controller, su ch as an smsc sio, through the smbus. the smbus is a two-wire serial communication prot ocol between a computer host and its peripheral devices. a detailed timing diagram is shown in figure 4.1 . stretching of the smclk signal is supported, however the emc2103 will not stretch the clock signal. the emc2103 contains a single smbus interface. the emc2103 client inte rfaces are smbus 2.0 compatible and support send byte, read byte, rece ive byte and the alert response address as valid protocols. these protocols are used as shown below. all of the below protocols use the convention in ta b l e 4 . 1 . 4.2 write byte the write byte is used to write one byte of data to the registers as shown below table 4.2 : figure 4.1 smbus timing diagram table 4.1 protocol format data sent to device data sent to the host # of bits sent # of bits sent table 4.2 write byte protocol start slave address wr ack register address ack register data ack stop 0 -> 1 0101_110 0 0 0 -> 1 0 xxh 0 1 -> 0 smdata smclk t low t rise t high t fall t buf t hd:sta p s s - start condition p - stop condition t hd:dat t su:dat t su:sta t hd:sta p t su:sto s
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 18 smsc emc2103 datasheet 4.3 read byte the read byte protocol is used to read one byte of data from the registers as shown in table 4.3 . 4.4 send byte the send byte protocol is used to set the internal address register pointer to the correct address location. no data is transferred during the send byte protocol as shown in ta b l e 4 . 4 . 4.5 receive byte the receive byte protocol is used to read data from a register when the internal register address pointer is known to be at the right location (e.g. set via send byte). this is used for consecutive reads of the same register as shown in ta b l e 4 . 5 . 4.6 alert response address the alert output can be used as a processor interr upt or as an smbus alert when configured to operate as an interrupt. when it detects that the alert pin is asserted, the host will send the alert response address (ara) to the general address of 0001_100b. all devices wi th active interrupts will respond with their client address as shown in table 4.6 . table 4.3 read byte protocol start slave address wr ack register address ack start slave address rd ack register data nack stop 0 -> 1 0101_110 0 0 xxh 0 0 -> 1 0101_110 1 0 xxh 1 1 -> 0 table 4.4 send byte protocol start slave address wr ack register address ack stop 0 -> 1 0101_110 0 0 xxh 1 1 -> 0 table 4.5 receive byte protocol start slave address rd ack register data nack stop 0 -> 1 0101_110 1 0 xxh 1 1 -> 0 table 4.6 alert response address protocol start alert response address rd ack device address nack stop 0 -> 1 0001_100 1 0 0101_1100 1 1 -> 0
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 19 revision 0.85 (01-29-08) datasheet the emc2103 will respond to the ara in the following way if the alert pin is asserted. 1. send slave address and verify that full slav e address was sent (i.e. the smbus communication from the device was not prematurely stopped due to a bus contention event). 2. set the mask bit to clear the alert pin. 4.7 smbus address the emc2103 smbus address is fixed at 0101_110xb. other addresses are available. contact smsc for details. attempting to communicate with t he emc2103 smbus interface with an invalid slave address or invalid protocol will result in no response from the de vice and will not affect its register contents. 4.8 smbus time-out the emc2103 includes an smbus time -out feature. following a 30ms period of inactivity on the smbus, the device will time-out and reset the smbus interface.
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 20 smsc emc2103 datasheet chapter 5 general description the emc2103 is an smbus compliant fan controller with one external (emc2103-2 offers up to three external diode channels) and one internal temperat ure channels. the fan driv er can be operated using two methods each with two modes. the methods include an rpm based fan speed control algorithm and a direct pwm drive setting. the modes include manually programming the desired settings or using the internal programmable temperature look- up table to select the desired setting based on measured temperature. the temperature monitors offer 1c accuracy (for external diodes) with sophisticated features to reduce errors introduced by series resistance and beta variation of substrate thermal diode transistors commonly found in processors (including support of the bjt or transistor model for a cpu diode). the emc2103 allows the user to program temperatur es generated from external sources to control the fan speed. this functionality also supports dt s data from the cpu. by pushing dts or standard temperature values into dedicated registers, t he external temperature readings can be used in conjunction with the external diode(s) and in ternal diode to control the fan speed. the emc2103 also includes a hardware progra mmable temperature limit and dedicated system shutdown output for thermal protec tion of critical circuitry. figure 5.1 shows a system diagr am of the emc2103. figure 5.1 system diagram for emc2103 cpu host smbus interface dp1 dn1 smdata thermal diode emc2103 smclk pwm alert fan drive circuitry tach dp2 / dn3* dn2 / dp3* * denotes emc2103-2 only sys_shdn vdd vdd optional anti- parallel diode 1.5v 1.2k trip_set vdd vdd gpio2* gpio1*
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 21 revision 0.85 (01-29-08) datasheet 5.1 critical/thermal shutdown the emc2103 provides a hardware critical /thermal shutdown function for systems. figure 5.2 is a block diagram of this critical/thermal shutdown function. the critical/thermal shutdown function accepts configuration information from the fixed states of the shdn_sel pin as described in section 5.1.1 . each of the software programmed temperature limits can be optionally configured to act as inputs to the critical / thermal shutdown independent of t he hardware shutdown operation. when configured to operate this way, the sys_shdn# pin will be asse rted when the temperature meets or exceeds the limit. the pin will be released when the temperature drops below the limit however the individual status bits will not be cleared if set (see section 6.13 ). the analog portion of the critical/thermal shutdown function monitors the hardware determined shutdown channel (see section 5.1.1 ). this measured temperature is then compared with trip_set point. this trip_set point is set by the system des igner with a single external resistor divider as described in section 5.1.2 . the sys_shdn is asserted when the indicated temper ature meets or exceeds the temperature threshold (t p ) established by the trip_set input pin for a number of cons ecutive measurements defined by the fault queue. if the hw_shdn output is asserted and the temperature drops below the threshold, then it will be set to a logic ?0? state. figure 5.2 block diagram of critical / thermal shutdown temperature conversion hw_shdn h/w thermal shutdown sensor critical / thermal shutdown smbus traffic sw_shdn sys_shdn temperature conversion software shutdown enable trip_set resistor decode vdd shdn_sel
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 22 smsc emc2103 datasheet 5.1.1 shdn_sel pin the emc2103 has a ?strappable? input (shdn_sel) allowing for configuration of the hardware critical/thermal shutdown input channel. the pull-up resistor used on this pin identifies which configuration setting is used as shown in ta b l e 5 . 1 . . note 5.1 for the emc2103-1, the decode for a 22k ohm resistor on the shdn_sel pin will be to use the external diode 1 channel in diode mode (the same as the decode for a 6.8k ohm resistor) as the hardware shutdown device. 5.1.2 trip_set pin the emc2103?s trip_set pin is an analog input to the critical/thermal shutdown block which sets the thermal shutdown temperature. the system desi gner creates a voltage level at the input through a simple resistor connected to gnd as shown in figure 5.2 . the value of this resistor is used to create an input voltage on the trip_set pin which is tr anslated into a temperature ranging from 65c to 127c as shown in table 5.2 application note: current only flows when the trip_set pin is being monitored. at all other times, the internal reference voltage is removed and the trip_set pin will be pulled down to ground. application note: the trip_set pin circuitry is designed to use a 1% resistor externally. using a 1% resistor will result in the thermal / critical shutdown temperature being decoded correctly. if a 5% resistor is used, then the thermal / critic al shutdown temperature may be decoded with as much as 1c error. table 5.1 shdn_sel pin decode pull up resistor mode of operation configuration mechanism < 4.7k ohm external diode 1 simple mode - beta compensation disabled, rec disabled - recommended for amd cpu diodes host control via smbus 6.8k ohm external diode 1 diode mode - beta compensation disabled, rec enabled host control via smbus 10k ohm external diode 1 transistor mode - beta compensation enabled, rec enabled - recommended for intel 45nm and 65mn cpu diodes host control via smbus 15k ohm internal diode host control via smbus 22k ohm external diode 2 transistor mode - beta compensation enabled, rec enabled (emc2103-2 only) see note 5.1 host control via smbus > 33k ohm external diode 1 transistor mode - beta compensation enabled, rec enabled host control via smbus
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 23 revision 0.85 (01-29-08) datasheet table 5.2 trip_set resistor setting t trip (c) rset (1%) t trip (c) rset (1%) 65 0.0 97 1240 66 28.7 98 1330 67 48.7 99 1400 68 69.8 100 1500 69 90.9 101 1580 70 113 102 1690 71 137 103 1820 72 158 104 1960 73 182 105 2050 74 210 106 2210 75 237 107 2370 76 261 108 2550 77 294 109 2740 78 324. 110 2940 79 348 111 3160 80 383 112 3480 81 412 113 3740 82 453 114 4120 83 487 115 4530 84 523 116 4990 85 562 117 5490 86 604 118 6040 87 649 119 6810 88 698 120 7870 89 750 121 9090 90 787 122 10700 91 845 123 12700 92 909 124 15800 93 953 125 20500 94 1020 126 29400 95 1100 127 49900 96 1150 65 open
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 24 smsc emc2103 datasheet 5.2 fan control modes of operation the emc2103 has four modes of oper ation for the fan driver. each mode uses ramp rate control and the spin up routine 1. pwm setting mode - in this mode of operation, the user directly controls the pwm duty cycle setting. updating the fan dr iver setting register (see section 6.20 ) will instantly update the fan drive. ? this is the default mode. the pwm setting m ode is enabled by clearing both the en_algo bit in the fan configuration register (see section 6.22 ) and the lut_lock bit in the look up table configuration register (see section 6.32 ). ? whenever the pwm setting mode is enabled the current drive will be changed to what was last written into the fan driver setting register. 2. fan speed control mode (fsc) - in this mode of operation, the user determines a fan speed and the drive setting is automatically updated to achieve this target speed. ? this mode is enabled by clearing the lut_lock bit in the look up table (lut) configuration register and setting the en_a lgo bit in the fan configuration register. 3. using the look up table with fan drive settings (pwm setting w/ lut mode) - in this mode of operation, the user programs the look up table with pwm duty cycle settings and corresponding temperature thresholds. the fan drive is se t based on the measured temperatures and the corresponding drive settings. ? this mode is enabled by programming the l ook up table then setting the lut_lock bit while the rpm / pwm bit is set to a ?1? (see section 6.32 ) 4. using the look up table with fan speed contro l algorithm (fsc w/ lut mode)- in this mode of operation, the user programs the look up tabl e with fan speed target values and corresponding temperature thresholds. the tach target register will be set based on the measured temperatures and the correspondi ng target settings. the pwm dr ive settings will be determined automatically based on the rpm based fan speed control algorithm ? this mode is enabled by programming the l ook up table then setting the lut_lock bit while the rpm / pwm bit is set to ?0? (see section 6.32 ). table 5.3 fan controls active for operating mode direct pwm setting mode fsc mode direct pwm setting w/ lut mode fsc w/ lut mode fan driver setting (read / write) fan driver setting (read only) fan driver setting (read only) fan driver setting (read only) edges[1:0] edges[1:0] (fan configuration) edges[1:0] edges[1:0] - range[1:0] (fan configuration) - range[1:0] (fan configuration) update[2:0] (fan configuration) update[2:0] (fan configuration) update[2:0] (fan configuration) update[2:0] (fan configuration) level (spin up configuration) level (spin up configuration) level (spin up configuration) level (spin up configuration) spinup_time[1:0] (spin up configuration) spinup_time[1:0] (spin up configuration) spinup_time[1:0] (spin up configuration) spinup_time[1:0] (spin up configuration) fan step fan step fan step fan step - fan minimum drive fan minimum drive
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 25 revision 0.85 (01-29-08) datasheet 5.3 pwm fan driver the emc2103 supports a high or low frequency pw m driver. the output can be configured as either push-pull or open drain and the frequency ranges from 9.5hz to 26khz in four programmable frequency bands. 5.4 fan control look-up table the emc2103 uses a look-up table to apply a user-programmable fan control profile based on measured temperature to the fan dr iver. in this look-up table, each temperature channel is allowed to control the fan drive output independently (or jointly) by programming up to eight pairs of temperature and drive setting entries. the user programs the look-up table based on the desired operation. if the rpm based fan speed control algorithm is to be used (see section 5.5 ), then the user must prog ram a fan speed target for each temperature setting of interest. alternately, if the rpm based fan speed control algorithm is not to be used, then the user must program a pwm se tting for each temperature setting of interest. if the measured temperature on the external diode c hannel meets or exceeds any of the temperature thresholds for any of the channels, the fan output will be automatically set to the desired setting corresponding to the exceeded temperature. in ca ses where multiple temperature channel thresholds are exceeded, the highest fan drive setting will take precedence. figure 5.3 shows an example of this behavior using a single channel. when the measured temperat ure drops to a point below a lower threshold minus the hysteresis value, the fan output will be set to t he corresponding lower set point. valid tach count valid tach count valid tach count valid tach count - tach target (read / write) - tach target (read only) tach reading tach reading tach reading tach reading - - look up table drive / temperature settings (read only) look up table drive / temperature settings (read only) - drive_fail_cnt [1:0] (spin up configuration) + fan drive fail band - drive_fail_cnt [1:0] (spin up configuration) + fan drive fail band table 5.3 fan controls active for operating mode (continued) direct pwm setting mode fsc mode direct pwm setting w/ lut mode fsc w/ lut mode
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 26 smsc emc2103 datasheet 5.4.1 programming the look up table when the look up table is used, it must be l oaded and configured correct ly based on the system requirements. the following steps outline the procedure. 1. determine whether the look up table will drive a pwm duty cycle or a tachometer target value and set the rpm / pwm bit in the f an lut configuration register (see section 6.32 ). 2. determine which measurement channels (up to fou r) are to be used with the look up table and set the temp3_cfg and temp4_cfg bits accordingly in the fan lut configuration register. 3. for each step to be used in the lut, set the fan setting (either pwm or tach target as set by the rpm / pwm bit). if a setting is not used, then set it to ffh (if a pwm) or 00h (if a tach target). load the lowest settings first in ascending orde r (i.e. fan setting 1 is the lowest setting greater than ?off?. fan setting 2 is the ne xt highest setting, etc.). see section 6.33 . 4. for each step to be used in the lut, set each of the measurement channel thresholds. these values must be set in the same data format that th e data is presented. if dts is to be used, then the format should be in temperature with a maximum threshold of 100c (64h). if a measurement channel is not used, then set the threshold at ffh. 5. update the threshold hysteresis to be smaller than the smallest table step. 6. configure the rpm based fan speed contro l algorithm if it is to be used. see section 5.5.1 for more details. figure 5.3 fan control look-up table example time fan setting temp s2 s3 s4 t4 t5 t6 averaged temperature t4 - hyst t5 - hyst t6 - hyst s1 t3 t3 - hyst t2 t2 - hyst s6 t1 s5 measurement taken fan setting
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 27 revision 0.85 (01-29-08) datasheet 7. set the lut_lock bit to enable the look up table and begin fan control in the fan lut configuration register. 5.4.2 dts support the emc2103 supports dts (intel?s digital temperature sensor) data in the fan control look up table. intel?s dts data is a positive number that represents the processor?s relative temperature below a fixed value called t control which is generally equal to 100c for intel mobile processors. for example, a dts value of 10c means that the ac tual processor temperature is 10c below t control or equal to 90c. either or both of the pushed temp erature registers can be written with dts data and used to control the fan driver. when dts data is entered, then the use_dts_fx bit must be set in the fan lut configuration register. once this bit is set, the dt s data entered is automatically subtracted from a value of 100c. this delta value is then used in the look up table as standard temperature data. application note: the device is designed with the assumption that t control is 100c. as such, all dts related conversions are done based on this value including look up table comparisons. if t control is adjusted (i.e. t control is shifted to 105c), then all of the look up table thresholds should be adjusted by a value equal to t control - 100c. 5.5 rpm based fan speed control algorithm (fsc) the emc2103 includes an rpm based fan speed control algorithm. this fan control algorithm uses proportional, integral, and derivative terms to automatically approach and maintain the system?s desired fan speed to an accuracy directly propor tional to the accuracy of the clock source. figure 5.4 shows a simple flow diagram of the rpm based fan speed control algorithm operation. the desired tachometer co unt is set by the user inputting t he desired number of 32.768khz cycles that occur per fan revolution. this is done by eith er manually setting the ta ch target register or by programming the temperature look-u p table. the user may change the target count at any time. the user may also set the target count to ffh in order to disable the fan driver for lower current operation. for example, if a desired rpm rate for a 2-pole fan is 3000 rpm then the user would input the hexidecimal equivalent of 1296 (51h in the tach targ et register). this number represents the number of 32.768khz cycles that would occu r during the time it takes the fan to complete a single revolution when it is spinning at 3000rpms. see section 6.30 for rpm -> tach calculations or appendix b for a complied table showing this information (for default conditions). the emc2103?s rpm based fan speed control algo rithm has programmable configuration settings for parameters such as ramp-rate control and spin up conditions. th e fan driver autom atically detects and attempts to alleviate a stalled/stuck fan condition while also asserting the alert pin. the emc2103 works with fans that op erate up to 16,000 rpms and prov ides a valid tachometer signal.
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 28 smsc emc2103 datasheet 5.5.1 programming the rpm based fan speed control algorithm the rpm based fan speed control algorithm powers -up disabled. the following registers control the algorithm. the emc2103 fan control registers are pre-loaded with defaults that will work for a wide variety of fans so only the tach ta rget register is required to set a fan speed. the other fan control registers can be used to fine-tune the algorith m behavior based on application requirements. note that steps 1 - 7 are optional and need only be performed if the default settings do not provide the desired fan response. 1. set the valid tach count register to maximum number of tach counts to indicate the fan is spinning. 2. set the spin up configuration register to the spin up level and spin time desired. figure 5.4 rpm based fan speed control algorithm set tach target count tach reading = tach target? spin up required ? perform spin up routine m aintain fan drive tach reading < tach target? reduce fan drive increase fan drive measure fan speed yes no yes no yes no ram p rate control
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 29 revision 0.85 (01-29-08) datasheet 3. set the fan step register to the desired step size. 4. set the fan minimum drive register to the minimum drive value that will maintain fan operation. 5. set the update time, and edges options in the fan configuration register. 6. set the valid tach count setting at the highest count that indicates that the fan is spinning. 7. set the tach target register to the desired tachometer count. 8. enable the rpm based fan speed control algorithm by setting the en_algo bit. 5.6 tachometer measurement the tachometer measurement circui try is used in conjunction with the rpm based fan speed control algorithm to update the fan driver output. addition ally, it can be used in direct setting mode as a diagnostic for host based fan control. this method monitors the tach signal in real ti me. it constantly updates the tachometer measurement by reporting the number of clocks between a user programmed number of edges on the tach signal (see ta b l e 8 . 5 ) using the tach period measurement method provi des fast response times for the rpm based fan speed control algorithm and the data is presented as a count value that represents the fan rpm period. when this method is used, all fan target values must be input as a count value for proper operation. application note: the tach period measurement method works independently of the drive settings. if the device is put into direct setting and the fan drive is set at a le vel that is lower than the fan can operate (including zero drive), then the ta chometer measurement may signal a stalled fan condition and assert an interrupt. 5.6.1 stalled fan a stalled fan is detected differently based on which tach method is enabled. if the tach period measurement measurement method is implemented, and if the tach counter exceeds the user- programmable valid tach count setting then it will flag the fan as stalled and trigger an interrupt. if the rpm based fan speed control algorithm is enabled, the algorithm will automatically attempt to restart the fan until it detects a valid tachometer level or is disabled. the fan_stall status bit indicates that a stalled fan was detected. this bi t is checked conditionally depending on the mode of operation. ? when the direct setting mode or direct setting with lut mode are enabled or the spin up routine is initiated, the fan_stall interrupt will be ma sked for the duration of the programmed spin up time (see ta b l e 8 . 1 6 ). this is to allow the fan opportunity to reach a valid speed without generating unnecessary interrupts. ? when the direct setting mode or direct setting w/ lut mode are activa ted then whenever the tach reading register value exceeds the valid tach count register setting, the fan_stall status bit will be set. ? when using the rpm based fan speed control algorithm (either fsc mode or lut with fsc mode), the stalled fan condition is checked whene ver the update time is met and the fan drive setting is updated. it is not a continuous check. 5.6.2 aging fan or in valid drive detection the emc2103 contains circuitry th at detects that the programmed fan speed can be reached by the fan. if the target fan speed cannot be reached with in a user defined band of tach counts at maximum drive then the drive_fail st atus bit is and the alert pin is asserted. this is useful to detect aging fan conditions (where the fan?s natural maximum sp eed degrades over time) or incorrect fan speed settings.
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 30 smsc emc2103 datasheet 5.7 spin up routine the emc2103 also contains programmable circuitry to control the spin up behavior of the fan driver to ensure proper fan operation. the spin up routin e is initiated under the following conditions when the tach period measurement method of tach measur ement is used. this applies to either the rpm based fan speed control algorithm mode or the di rect setting mode (with or without the look up table). 1. the tach target register value changes from a value of ffh to a value that is less than the valid tach count (see section 8.10 and section 8.12 ). 2. the rpm based fan speed control algorithm?s m easured tach reading register value is greater than the valid tach count setting. when the spin up routine is operating, the fan driv er is set to full scale (optional) for one quarter of the total user defined spin up time. for the remaining spin up time, the fan driver output is set a a user defined level (30% through 65% drive). after the spin up routine has finished, the emc2103 measures the tach signal. if the measured tach reading register value is higher than the valid tach count register setting, the fan_spin status bit is set and the spin up routine will automatically attempt to restart the fan. figure 5.5 shows an example of the spin up routine in response to a programmed fan speed change based on the first condition above. figure 5.5 spin up routine 100% (optional) 30% through 65% algorithm controlled drive fan step spin up time ? of spin up time update time target count changed target count reached new target count prev target count = ffh check tach
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 31 revision 0.85 (01-29-08) datasheet 5.8 ramp rate control the pwm output drive can be configured with automa tic ramp rate control. if the rpm based fan speed control algorithm is used, then this ramp ra te control is automatically used based on the fan control derivative option settings. see section 6.23, "fan conf iguration 2 register" . the user programs a maximum step size for the pwm setting and an u pdate time. the update time varies from 100ms to 1.6s while the pwm maximum step can vary from 1 pwm count to 31 pwm counts. when a new pwm is entered, the delta from the next pwm and the previous pwm is determined. if this delta is greater than the max step settings, then the pwm is incrementally adjusted every 100ms to 1.6s as determined by the update time until the target pwm setting is reached. see figure 5.6 . 5.9 watchdog timer the emc2103 contains an internal watchdog timer. once the device has powered up the watchdog timer monitors the bus traffic for signs of activity. the watchdog timer starts when the internal supply has reached its operating point. the watchdog time r only starts immediately after power-up and once it has been triggered or d eactivated will not restart. if four (4) seconds elapse withou t the system host programming the device, then th e watchdog will be triggered and the following will occur: 1. the watch status bit will be set. 2. the fan driver will be set to full scale drive. it will remain at full scale drive until one of the three conditions listed below are met. if the watchdog timer is triggered, the following three operations will disable the timer and return the device to normal operation. alter nately, if the watchdog timer has not yet been triggered performing any one of the following will disable it. 1. writing the fan setting register will disable the watchdog timer. 2. enabling the rpm based fan speed control algorithm by setting the en_algo bit will disable the watchdog timer. the fan driver will be set based on the rpm based fan speed control algorithm. figure 5.6 ramp rate control previous setting next desired setting max step max step update time update time setting changed
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 32 smsc emc2103 datasheet 3. setting the lut_lock bit will disable the watchdo g timer. the fan driver will be set based on the look up table settings. writing any other configuration register s will not disable the watchdog timer. application note: disabling the watchdog will not automatically set the fan drive. this must be done manually (or via the look up table). 5.10 fault queue the emc2103 contains a programmable fault queue on all fault conditions. the fault queue defines how many consecutive out-of-limit conditions must be reported before the corr esponding status bit is set (and the alert pin asserted). 5.11 temperature monitoring the emc2103 can monitor the temperature of up to three (3) externally connected diodes as well as the internal or ambient temperature. each channel is configured with the following features enabled or disabled based on user settings and system requirements. 5.11.1 dynamic averaging the emc2103 supports dynamic averaging. when enable d, this feature changes the conversion time for all channels based on the selected conversion ra te. this essentially increases the averaging factor as shown in ta b l e 5 . 4 . the benefits of dynamic averaging are improved noise rejection due to the longer integration time as well as less ran dom variation on the temperature measurement. 5.11.2 resistance error correction the emc2103 includes active resistance error correction to remove the effect of up to 100 ohms of series resistance. without this aut omatic feature, voltage developed across the parasitic resistance in the remote diode path causes the temperature to read higher than the true temperature is. the error induced by parasitic resistance is approximately +0 .7c per ohm. sources of parasitic resistance include bulk resistance in the remote temperature transistor junctions, series resistance in the cpu, and resistance in the printed circuit board traces and package leads. resistance error correction in the emc2103 eliminates the need to characterize and compensate for parasitic resistance in the remote diode path. table 5.4 dynamic averaging behavior conversion rate averaging factor (relative to 11-bit conversi0n) dynamic averaging enabled dynamic averaging disabled 1 / sec 8x 1x 2 / sec 4x 1x 4 / sec 2x 1x continuous 1x 1x
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 33 revision 0.85 (01-29-08) datasheet 5.11.3 beta compensation the forward current gain, or beta, of a transistor is not constant as emitter currents change. as well, it is not constant over changes in temperature. the variation in beta causes an error in temperature reading that is proportional to absolute temperatur e. this correction is done by implementing the bjt or transistor model for temperature measurement. for discrete transistors configured with the collect or and base shorted together, the beta is generally sufficiently high such that the percent change in beta variation is very small. for example, a 10% variation in beta for two forced emitter currents with a transistor whose ideal beta is 50 would contribute approximately 0.25c error at 100c. however for s ubstrate transistors where the base-emitter junction is used for temperature measurement and the collector is tied to the substrate, the proportional beta variation will cause large error. for example, a 10% variation in beta for two forced emitter currents with a transistor whose ideal beta is 0.5 would contribute approximately 8.25c error at 100c. the beta compensation circuitry in the emc2103 corrects for this beta variation to eliminate any error which would normally be induced. it automatically detects the appropriate beta setting to use. 5.11.4 digital averaging the external diode channels support a 4x digital aver aging filter. every cycle, this filter updates the temperature data based an a runnin g average of the last 4 measured temperature values. the digital averaging reduces temperature flickering and increases temperature measurement stability. the digital averaging can be disabled by setting the dis_avg bit in the configuration 2 register (see section 6.11 ). 5.12 diode connections the external diode 1 channel can support a diode- connected transistor (such as a 2n3904) or a substrate transistor requiring the bjt or transistor model (such as those found in a cpu or gpu) as shown in figure 5.7 . the external diode 2 channel supports any diode connection shown or it can be configured to operate in anti-parallel diode (apd) mode. when configur ed in apd mode, a third temperature channel is available that shares the dp2 and dn2 pins. when in this mode, both the external diode 2 channel and external diode 3 channel thermal diodes must be connected as diodes. figure 5.7 diode connections local ground to dp typical remote substrate transistor i.e. cpu substrate pnp typical remote discrete pnp transistor i.e. 2n3906 typical remote discrete npn transistor i.e. 2n3904 to dn to dp to dn to dp to dn
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 34 smsc emc2103 datasheet 5.12.1 diode faults the emc2103 actively detects an open and short condition on each measurement channel. when a diode fault is detected, the temperature data msbyte is forced to a value of 80h and the fault bit is set in the status register. when the external dio de 2 channel is configured to operate in apd mode, the circuitry will detect independent open fault cond itions, however a short condition will be shared between the external diode 2 and external diode 3 channels. if a diode fault occurs on the har dware defined shutdown channel, then no temperature comparison is performed. the sys_shdn pin will not be asserted. 5.13 gpios the emc2103-2 contains two dedicated gpio pins. th e gpio pins can be individually configured as an input or an output and as a push-pull or open- drain output. additionally, each gpio pin, when configured as an input, can be individually enabled to trigger an interrupt when they change states.
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 35 revision 0.85 (01-29-08) datasheet chapter 6 register set 6.1 register map the following registers are accessible through the smbu s interface. all register bits marked as ?-? will always read ?0?. a write to these bits will have no effect. application note: all registers denoted with a ** are specific to th e emc2103-2 only. writing to these registers by the emc2103-1 will have no affect and reading from them will return ?00h?. table 6.1 emc2103 register set addr r/w register name function default value lock page temperature registers 00h r internal temp reading high byte stores the integer data of the internal diode 00h no page 42 01h r internal temp reading low byte stores the fractional data of the internal diode 00h no page 42 02h r external diode 1 temp reading high byte stores the integer data of external diode 1 00h no page 42 03h r external diode 1 temp reading low byte stores the fractional data of external diode 1 00h no page 42 04h ** r external diode 2 temp reading high byte ** stores the integer data of external diode 2 00h no page 42 05h ** r external diode 2 temp reading low byte ** stores the fractional data of external diode 2 00h no page 42 06h ** r external diode 3 temp reading high byte ** stores the integer data of external diode 3 00h no page 42 07h ** r external diode 3 temp reading low byte ** stores the fractional data of external diode 3 00h no page 42 0ah r critical/thermal shutdown temperature stores the calculated critical/thermal shutdown temperature high limit derived from trip_set pin voltage n/a no page 43 0ch r/w pushed temperature 1 stores the integer data for pushed temperature 1 to drive the lut 00h no page 43 0dh r/w pushed temperature 2 stores the integer data for pushed temperature 2 to drive the lut 00h no page 43 10h r trip_set voltage stores the measured voltage on the trip_set pin ffh no page 44
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 36 smsc emc2103 datasheet diode configuration 11h r/w external diode 1 ideality register stores the ideality factor used for external diode 1 12h swl page 44 12h ** r/w external diode 2 ideality register ** stores the ideality factor used for external diode 2 and external diode 3 12h swl page 44 14h r/w external diode 1 beta configuration configures the beta compensation settings for external diode 1 10h swl page 45 15h ** r/w external diode 2 beta configuration ** configures the beta compensation settings for external diode 2 10h swl page 45 17h r/w external diode rec configuration configures the resistance error correction functionality for all external diodes 07h swl page 46 19h r/w once external diode 1 tcrit limit stores the critical temperature limit for external diode 1 64h (100c) write once page 47 1ah ** r/w once external diode 2 tcrit limit ** stores the critical temperature limit for external diode 2 64h (100c) write once page 47 1bh ** r/w once external diode 3 tcrit limit ** stores the critical temperature limit for external diode 3 64h (100c) write once page 47 1dh r/w once internal diode tcrit limit stores the critical temperature limit for the internal diode 64h (100c) write once page 47 configuration and control 1fh r tcrit status stores the status bits for all temperature channel tcrit limits 00h no page 50 20h r/w configuration configure s the thermal / critical shutdown masking options 00h swl page 47 21h r/w configuration 2 controls the conversion rate for monitoring of all channels 0eh swl page 48 23h r-c interrupt status stores the status bits for temperature channels 00h no page 49 24h r-c high limit status stores the status bits for all temperature channel high limits 00h no page 50 25h r-c low limit status stores the status bits for all temperature channel low limits 00h no page 50 26h r-c diode fault stores the status bits for all temperature channel diode faults 00h no page 50 27h r-c fan status stores the status bits for the rpm based fan speed control algorithm 00h no page 51 28h r/w interrupt enable register controls the masking of interrupts on all temperature channels 00h no page 51 29h r/w fan interrupt enable register controls the masking of interrupts for the fan driver 00h no page 52 table 6.1 emc2103 regi ster set (continued) addr r/w register name function default value lock page
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 37 revision 0.85 (01-29-08) datasheet 2ah r/w pwm config configures the pwm driver 00h no page 52 2bh r/w pwm base frequency controls the base frequency of the pwm driver 03h no page 53 temperature limit registers 30h r/w external diode 1 temp high limit high limit for external diode 1 55h (+85c) swl page 53 31h ** r/w external diode 2 temp high limit ** high limit for external diode 2 55h (+85c) swl page 53 32h ** r/w external diode 3 temp high limit ** high limit for external diode 3 55h (+85c) swl page 53 34h r/w internal diode high limit high limit for internal diode 55h (85c) swl page 53 38h r/w external diode 1 temp low limit low limit for external diode 1 00h (0c) swl page 53 39h ** r/w external diode 2 temp low limit ** low limit for external diode 2 00h (0c) swl page 53 3ah ** r/w external diode 3 te m p l o w l i m i t * * low limit for external diode 3 00h (0c) swl page 53 3ch r/w internal diode low limit low limit for internal diode 00h (0c) swl page 53 fan control registers 40h r/w fan setting always displays the most recent fan driver input setting for fan. if the rpm based fan speed control algorithm is disabled, allows direct user control of the fan driver. 00h no page 54 41h r/w pwm divide stores the divide ratio to set the frequency for the fan 01h no page 54 42h r/w fan configuration 1 sets configuration values for the rpm based fan speed control algorithm for the fan 2bh no page 55 43h r/w fan configuration 2 sets additional configuration values for the fan driver 38h swl page 56 45h r/w gain holds the gain terms used by the rpm based fan speed control algorithm for the fan 2ah swl page 58 46h r/w fan spin up configuration sets the configuration values for spin up routine of the fan driver 19h swl page 58 47h r/w fan step sets the maximum change per update for the fan 10h swl page 60 48h r/w fan minimum drive sets the minimum drive value for the the fan driver 66h (40%) swl page 60 table 6.1 emc2103 regi ster set (continued) addr r/w register name function default value lock page
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 38 smsc emc2103 datasheet 49h r/w fan valid tach count holds the minimum tachometer reading that indicates the fan is spinning properly f5h swl page 61 4ah r/w fan drive fail band low byte stores the number of tach counts used to determine how the actual fan speed must match the target fan speed at full scale drive 00h swl page 61 4bh r/w fan drive fail band high byte 00h swl 4ch r/w tach target low byte holds the target tachometer reading low byte for the fan f8h no page 62 4dh r/w tach target high byte holds the target tachometer reading for the fan ffh no page 62 4eh r tach reading high byte holds the tachometer reading for the fan ffh no page 62 4fh r tach reading low byte holds the tachometer reading low byte for the fan f8h no page 62 look up table (lut) 50h r/w lut configuration stores and controls the configuration for the lut 00h no page 63 51h r/w lut drive 1 stores th e lowest programmed drive setting for the lut fbh lut lock page 64 52h r/w lut temp 1 setting 1 stores the threshold level for the external diode 1 channel that is associated with the drive 1 value 7fh (127c) lut lock page 64 53h r/w lut temp 2 setting 1 stores the threshold level for the external diode 2 channel that is associated with the drive 1 value 7fh (127c) lut lock page 64 54h r/w lut temp 3 setting 1 stores the threshold level for the external diode 3 channel (or pushed temp 1 temp) that is associated with the drive 1 value 7fh (127c) lut lock page 64 55h r/w lut temp 4 setting 1 stores the threshold level for the internal diode channel (or pushed temp 2 temp) that is associated with the drive 1 value 7fh (127c) lut lock page 64 56h r/w lut drive 2 stores the second programmed drive setting for the lut e6h lut lock page 64 57h r/w lut temp 1 setting 2 stores the threshold level for the external diode 1 channel that is associated with the drive 2 value 7fh (127c) lut lock page 64 58h r/w lut temp 2 setting 2 stores the threshold level for the external diode 2 channel that is associated with the drive 2 value 7fh (127c) lut lock page 64 59h r/w lut temp 3 setting 2 stores the threshold level for the external diode 3 channel (or pushed temp 1 temp) that is associated with the drive 2 value 7fh (127c) lut lock page 64 table 6.1 emc2103 regi ster set (continued) addr r/w register name function default value lock page
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 39 revision 0.85 (01-29-08) datasheet 5ah r/w lut temp 4 setting 2 stores the threshold level for the internal diode channel (or pushed temp 2 temp) that is associated with the drive 2 value 7fh (127c) lut lock page 64 5bh r/w lut drive 3 stores the third programmed drive setting for the lut d1h lut lock page 64 5ch r/w lut temp 1 setting 3 stores the threshold level for the external diode 1 channel that is associated with the drive 3 value 7fh (127c) lut lock page 64 5dh r/w lut temp 2 setting 3 stores the threshold level for the external diode 2 channel that is associated with the drive 3 value 7fh (127c) lut lock page 64 5eh r/w lut temp 3 setting 3 stores the threshold level for the external diode 3 channel (or pushed temp 1 temp) that is associated with the drive 3 value 7fh (127c) lut lock page 64 5fh r/w lut temp 4 setting 3 stores the threshold level for the internal diode channel (or pushed temp 2 temp) that is associated with the drive 3 value 7fh (127c) lut lock page 64 60h r/w lut drive 4 stores the fourth programmed drive setting for the lut bch lut lock page 64 61h r/w lut temp 1 setting 4 stores the threshold level for the external diode 1channel that is associated with the drive 4 value 7fh (127c) lut lock page 64 62h r/w lut temp 2 setting 4 stores the threshold level for the external diode 2 channel that is associated with the drive 4 value 7fh (127c) lut lock page 64 63h r/w lut temp 3 setting 4 stores the threshold level for the external diode 3 channel (or pushed temp 1 temp) that is associated with the drive 4 value 7fh (127c) lut lock page 64 64h r/w lut temp 4 setting 4 stores the threshold level for the internal diode channel (or pushed temp 2 temp) that is associated with the drive 4 value 7fh (127c) lut lock page 64 65h r/w lut drive 5 stores the fifth programmed drive setting for the lut a7h lut lock page 64 66h r/w lut temp 1 setting 5 stores the threshold level for the external diode 1 channel that is associated with the drive 5 value 7fh (127c) lut lock page 64 67h r/w lut temp 2 setting 5 stores the threshold level for the external diode 2 channel that is associated with the drive 5 value 7fh (127c) lut lock page 64 68h r/w lut temp 3 setting 5 stores the threshold level for the external diode 3 channel (or pushed temp 1 temp) that is associated with the drive 5 value 7fh (127c) lut lock page 64 table 6.1 emc2103 regi ster set (continued) addr r/w register name function default value lock page
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 40 smsc emc2103 datasheet 69h r/w lut temp 4 setting 5 stores the threshold level for the internal diode channel (or pushed temp 2 temp) that is associated with the drive 5 value 7fh (127c) lut lock page 64 6ah r/w lut drive 6 stores the sixth programmed drive setting for the lut 92h lut lock page 64 6bh r/w lut temp 1 setting 6 stores the threshold level for the external diode 1 channel that is associated with the drive 6 value 7fh (127c) lut lock page 64 6ch r/w lut temp 2 setting 6 stores the threshold level for the external diode 2 channel that is associated with the drive 6 value 7fh (127c) lut lock page 64 6dh r/w lut temp 3 setting 6 stores the threshold level for the external diode 3 channel (or pushed temp 1 temp) that is associated with the drive 6 value 7fh (127c) lut lock page 64 6eh r/w lut temp 4 setting 6 stores the threshold level for the internal diode channel (or pushed temp 2 temp) that is associated with the drive 6 value 7fh (127c) lut lock page 64 6fh r/w lut drive 7 stores the seventh programmed drive setting for the lut 92h lut lock page 64 70h r/w lut temp 1 setting 7 stores the threshold level for the external diode 1 channel that is associated with the drive 7 value 7fh (127c) lut lock page 64 71h r/w lut temp 2 setting 7 stores the threshold level for the external diode 2 channel that is associated with the drive 7 value 7fh (127c) lut lock page 64 72h r/w lut temp 3 setting 7 stores the threshold level for the external diode 3 channel (or pushed temp 1 temp) that is associated with the drive 7 value 7fh (127c) lut lock page 64 73h r/w lut temp 4 setting 7 stores the threshold level for the internal diode channel (or pushed temp 2 temp) that is associated with the drive 7 value 7fh (127c) lut lock page 64 74h r/w lut drive 8 stores the highest programmed drive setting for the lut 92h lut lock page 64 75h r/w lut temp 1 setting 8 stores the threshold level for the external diode 1 channel that is associated with the drive 8 value 7fh (127c) lut lock page 64 76h r/w lut temp 2 setting 8 stores the threshold level for the external diode 2 channel that is associated with the drive 8 value 7fh (127c) lut lock page 64 77h r/w lut temp 3 setting 8 stores the threshold level for the external diode 3 channel (or pushed temp 1 temp) that is associated with the drive 8 value 7fh (127c) lut lock page 64 table 6.1 emc2103 regi ster set (continued) addr r/w register name function default value lock page
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 41 revision 0.85 (01-29-08) datasheet during power-on-reset (por), the default values are stored in the registers. a por is initiated when power is first applied to the part and the vo ltage on the vdd supply surpasses the por level as specified in the electrical charac teristics. any reads to undefined registers will return 00h. writes to undefined registers will not have an effect. 6.1.1 lock entries the lock column describes the locking mechanism, if any, used for individual registers. all swl registers are software locked and therefore made read-only when the lock bit is set. 78h r/w lut temp 4 setting 8 stores the threshold level for the internal diode channel (or pushed temp 2 temp) that is associated with the drive 8 value 7fh (127c) lut lock page 64 79h r/w lut temp hysteresis stores the hysteresis that is shared for all temperature inputs 0ah (10c) lut lock page 64 e1h ** r/w gpio direction register ** controls the gpio direction for gpios 1 and 2 00h no page 65 e2h ** r/w gpio output configuration register ** controls the output type of gpios 1 and 2 00h no page 66 e3h ** r/w gpio input register ** stores the inputs for gpios 1 and 2 00h no page 66 e4h ** r/w gpio output register ** controls the output state of gpios 1 and 2 00h no page 66 e5h ** r/w gpio interrupt enable register ** enables interrupts for gpios 1 and 2 00h no page 67 e6h ** r/w gpio status ** indicates when the gpios change state 00h no page 67 lock register ef r/w software lock locks a ll swl registers 00h swl page 68 revision registers fch r product features indicates which pin selected options are enabled 00h no page 68 fdh r product id emc2103-1 stores the unique product id 24h no page 69 product id emc2103-2 26h no feh r manufacturer id manufacturer id 5dh no page 69 ffh r revision revision 00h no page 69 table 6.1 emc2103 regi ster set (continued) addr r/w register name function default value lock page
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 42 smsc emc2103 datasheet 6.2 temperature data registers the temperature measurement range is from -64c to +127.875c. the data format is a signed two?s complement number as shown in table 6.3 . table 6.2 temperature data registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 00h r internal diode high byte sign 64 32 16 8 4 2 1 00h 01h r internal diode low byte 0.5 0.25 0.125 - - - - - 00h 02h r external diode 1 high byte sign 64 32 16 8 4 2 1 00h 03h r external diode 1 low byte 0.5 0.25 0.125 - - - - - 00h 04h ** r external diode 2 high byte ** sign 64 32 16 8 4 2 1 00h 05h ** r external diode 2 low byte ** 0.5 0.25 0.125 - - - - - 00h 06h ** r external diode 3 high byte ** sign 64 32 16 8 4 2 1 00h 07h ** r external diode 3 low byte ** 0.5 0.25 0.125 - - - - - 00h table 6.3 temperature data format temperature (c) binary hex (as read by registers) diode fault 1000_0000_000b 80_00h -63.875 1100_0000_001b c0_20h -63 1100_0001_000b c1_00h -1 1111_1111_000b ff_00h -0.125 1111_1111_111b ff_e0h 0 0000_0000_000b 00_00h 0.125 0000_0000_001b 00_20h 1 0000_0001_000b 01_00h 63 0011_1111_000b 3f_00h 64 0100_0000_000b 40_00h
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 43 revision 0.85 (01-29-08) datasheet 6.3 critical/thermal shut down temperature register the critical/thermal shutdown temper ature register is a read-only r egister that stores the voltage programmable threshold temperature used in the thermal / critical shutdown circuitry. the contents of the register reflect the calculated temperature determined by the voltage on the trip_set pin (see section 5.1.2 ). the data format is shown in ta b l e 6 . 5 . 6.4 pushed temperature registers 65 0100_0001_000b 41_00h 127 0111_1111_000b 7f_00h 127.875 0111_1111_111b 7f_e0h table 6.4 critical/thermal shutdown temperature register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 0ah r critical/thermal shutdown temperature 128 64 32 16 8 4 2 1 7fh (+127c) table 6.5 critical / thermal shutdown data format temperature (c) binary hex 0 0000_0000b 00h 1 0000_0001b 01h 63 0011_1111b 3fh 64 0100_0000b 40h 65 0100_0001b 41h 127 0111_1111b 7fh table 6.6 pushed temperature register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 0ch r/w pushed temperature 1 sign643216842100h 0dh r/w pushed temperature 2 sign643216842100h table 6.3 temperature data format (continued) temperature (c) binary hex (as read by registers)
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 44 smsc emc2103 datasheet the pushed temperature registers store user prog rammed temperature values that can be used by the look-up table to update the fan control algorithm . data written in these registers is not compared against any limits and must match the data format shown in table 6.3 . 6.5 trip_set voltage register the trip_set voltage register stores data that is measured on the trip_set voltage input. each bit weight represents mv of resolution so that the final voltage can be determined by adding the weighting of the set bits together. 6.6 ideality factor registers these registers store the ideality factors t hat are applied to the external diodes. the external diode 3 channel will use the settings for the external diode 2 channel. beta compensation and resistance error correction automatically correct for most diode ideality errors, therefore it is not recommended that th ese settings be updated without consulting smsc. only the lower three bits can be written. writing to any other bit will be ignored. the ideality factor regist ers are software locked. table 6.7 trip_set voltage register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 10h r/w trip_set voltage register 750.0 375.0 187.5 93.75 46.88 23.43 11.72 5.89 ffh table 6.8 ideality factor registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 11h r/w external diode 1 ideality 00010b2b1b012h 12h ** r/w external diode 2 ideality ** 00010b2b1b012h table 6.9 ideality factor look-up table setting factor 10h 1.0053 11h 1.0066 12h 1.0080 13h 1.0093 14h 1.0106 15h 1.0119
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 45 revision 0.85 (01-29-08) datasheet 6.7 beta configuration register the beta configuration register controls advanced temperature measurement features of the external diode channels. if external diode 1 is selected as the hardware shutdown measurement channel (see section 5.1.1 ) then the external diode 1 beta register will be read only. if the internal diode is selected, then this register can be written normally. likewise, if the external diode 2 channel is selected (emc2103-2 only) then this register can be written normally. fi nally, if external diode 2 is selected as the hardware shutdown measurement channel (emc2103-2 only), th en the external diode 2 beta configuration register will be read only. writing to a read only register will have no affect. the data will be ignored. bit 4 - autox - enables the automatic beta detection algorithm for the external diode x channel. ? ?0? - the automatic beta detection algorithm is disabled. the betax[3:0] bit settings will be used to control the beta compensation circuitry. ? ?1? (default) - the automatic beta detection algo rithm is enabled. the circuitry will automatically detect the transistor type and beta values and configure the betax[3:0] bits for optimal performance. bits 2 - 0 - betax[2:0] - hold a value that corresponds to a range of betas t hat the beta compensation circuitry can compensate for. these three bits w ill always show the current beta setting used by the circuitry. if the auto bit is set (default), then these bits may be overwritten with every temperature conversion. if the auto bit is not set, then the value of these bits is used to drive the beta compensation circuitry. in this case, these bits should be set with a value corresponding to the lowest expected value of beta for the pnp transisto r being used as a temperature sensing device. see table 6.11 for supported beta ranges. a value of 11 1b indicates that the beta compensation circuitry is disabled. in this condition, the diode channels will function with default current levels and will not automatically adjust for beta variation. th is mode is used when measuring a discrete 2n3904 transistor or amd thermal diode. if the external diode 3 channel is enabled, it will always use a beta setting of 111b. the beta configuration registers are software locked. 16h 1.0133 17h 1.0146 table 6.10 beta configuration register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 14h rw external diode 1 beta configuration --- aut o1 - beta1[2:0] 10h 15h ** r/w external diode 2 beta configuration ** --- aut o2 - beta2[2:0] 10h table 6.9 ideality factor look-up table (continued) setting factor
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 46 smsc emc2103 datasheet 6.8 rec configuration register the rec configuration register determines whether resistance error correction is used for each external diode channel. bit 2 - rec3 (emc2102-2 only)- controls the resist ance error correction functionality of external diode 3 (if enabled) ? ?0? - the rec functionality for external diode 3 is disabled ? ?1? (default) - the rec functionalit y for external diode 3 is enabled. bit 1 - rec2 (emc2103-2 only)- controls the resist ance error correction functionality of external diode 2. if external diode 2 is se lected as the hardware shutdown channel then this bit is read only and determined by the shdn_sel pin (see section 5.1.1 ). ? ?0? - the rec functionality for external diode 2 is disabled ? ?1? (default) - the rec functionalit y for external diode 2 is enabled. bit 0 - rec1 - indicates the resist ance error correction functionality of external diode 1. if external diode 1 is selected as the hardware shutdown channel then this bit is read only and determined by the shdn_sel pin (see section 5.1.1 ). ? ?0? - the rec functionality for external diode 1 is disabled ? ?1? (default) - the rec functionalit y for external diode 1 is enabled. the rec configuration register is software locked. table 6.11 beta compensation look up table betax[2:0] minimum beta 210 000 < 0.08 001 < 0.111 010 < 0.176 011 < 0.29 100 < 0.48 101 < 0.9 110 < 2.33 1 1 1 disabled table 6.12 rec configuration register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 17h r/w rec configuration -----rec3rec2rec1 07h
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 47 revision 0.85 (01-29-08) datasheet 6.9 critical temper ature limit registers the critical temperature limit regi sters store the critical temperatur e limit. at power up, none of the respective channels are linked to the sys_shdn pin or the hardware set t hermal/critical shutdown circuitry. whenever one of the registers is updated, two things occu r. first, the register is locked so that it cannot be updated again without a power on reset. second, t he respective temperature channel is linked to the sys_shdn pin and the hardware set thermal/critical shutdown circuitry. at this point, if the measured temperature channel exceeds the critical limit, the sys_shdn pin will be asserted, the appropriate bit set in the tcrit status register, and the tcrit bit in the interrupt status register will be set. 6.10 configuration register the configuration register controls the basic f unctionality of the emc2103. the bits are described below. bit 7 - mask - blocks the alert pin from being asserted. ? ?0? (default) - the alert pin is unmasked. if any bit in either status register is set, the alert pin will be asserted (unless individually masked via the mask register) ? ?1? - the alert pin is masked and will not be asserted. bit 3 - sys3 (emc2103-2 only) - enables the high temperature limit for the external diode 3 channel to trigger the critical / thermal shutdown circuitry (see section 5.1 ). ? ?0? (default) - the external diode 3 channel high limit will not be linked to the sys_shdn pin. if the temperature meets or exceeds the limit, the alert pin will be asserted normally. ? ?1? - the external diode 3 channel high limit will be linked to the sys_shdn pin. if the temperature meets or exceeds the limit then the sys_shdn pin will be asserted. the sys_shdn# pin will be released when the temperature drops below the high limit. the alert pin will be asserted normally. bit 2 - sys2 (emc2103-2 only) - enables the high temperature limit for the external diode 2 channel to trigger the critical / thermal shutdown circuitry (see section 5.1 ). table 6.13 limit registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 19h r/w once external diode 1 tcrit limit sign 64 32 16 8 4 2 1 64h (+100c) 1ah r/w once external diode 2 tcrit limit sign 64 32 16 8 4 2 1 64h (+100c) 1bh r/w once external diode 3 tcrit limit sign 64 32 16 8 4 2 1 64h (+100c) 1dh r/w once internal diode tcrit limit sign 64 32 16 8 4 2 1 64h (+100c) table 6.14 configuration register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 20h r/w configuration mask - - - sys3 sys2 sys1 apd 00h
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 48 smsc emc2103 datasheet ? ?0? (default) - the external diode 2 channel high limit will not be linked to the sys_shdn pin. if the temperature meets or exceeds the limit, the alert pin will be asserted normally. ? ?1? - the external diode 2 channel high limit will be linked to the sys_shdn pin. if the temperature meets or exceeds the limit then the sys_shdn pin will be asserted. the alert pin will be asserted normally. bit 1 - sys1 - enables the high temperature limit for the external diode 1 channel to trigger the critical / thermal shutdown circuitry (see section 5.1 ). ? ?0? (default) - the external diode 1 channel high limit will not be linked to the sys_shdn pin. if the temperature meets or e xceeds the limit, the alert pin will be asserted normally. ? ?1? - the external diode 1 channel high limit will be linked to the sys_shdn pin. if the temperature meets or exceeds the limit then the sys_shdn pin will be asserted. the alert pin will be asserted normally. bit 0 - apd (emc2103-2 only) - this bit enables the anti-parallel diode functionality on the external diode 3 pins (dp3 and dn3). ? ?0? (default) - the anti-parallel diode functionality is disabled. the external diode 2 channel can be configured for any type of diode ? ?1? - the anti-parallel diode functionality is en abled. both the external diode 2 and 3 channels are configured to support a diode or diode connected transistor (such as a 2n3904). application note: when the apd diode is enabled, there will be a delay of a full temperature update before any comparisons and functionality associat ed with the external diode 3 channel will be implemented. this includes the sys3 bit operat ion, limit comparisons, and look up table comparisons. the configuration register is software locked. 6.11 configuration 2 register the configuration 2 register cont rols conversion rate of the tem perature monitoring as well as the fault queue. bit 6 - dis_dyn - disables the dynamic averaging feature. ? ?0? (default) - the dynamic averaging function is enabled. the conversion time for all temperature channels is scaled based on the chosen conversion rate to maximize accuracy and immunity to random temperature measurement variation. ? ?1? - the dynamic averaging function is disabled. the conversion time for all temperature channels is fixed regardless of the chosen conversion rate. bit 5 - dis_to - disables the smbus time out function. ? ?0? (default) - the smbus time out function is enabled. ? ?1? - the smbus time out function is disabled allowing the device to be fully i 2 c compliant. bit 4 - dis_avg - disables digital averaging of the external diode channels. ? ?0? (default) - the external diode channels have digital averaging enabled. the temperature data is the average of the previous four measurements. table 6.15 configuration 2 register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 21h r/w config 2 - dis_d yn dis_ to dis_ avg queue[1:0] conv[1:0] 0eh
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 49 revision 0.85 (01-29-08) datasheet ? ?1? - the external diode channels have digital averag ing disabled. the temperat ure data is the last measured data. bits 3-2 - queue[1:0] - determines the number of consecutive out of limit conditions that are necessary to trigger an interrupt. each measurem ent channel has a separate fault queue associated with the high limit, low limit, and diode fault condition. application note: if the fault queue for any channel is currently active (i.e. an out of limit condition has been detected and caused the fault queu e to increment) then changing the settings will not take effect until the fault queue is zeroed. this occurs by the alert pin asserting or the out of limit condition being removed. bit 1 - 0 - conv[1:0] - determines the conversion ra te of the temperature monitoring. this conversion rate does not affect the fan driver. the supply cu rrent from vdd_3v is nominally dependent upon the conversion rate and the average current will in crease as the conversion rate increases. the configuration 2 register is software locked. 6.12 interrupt status register table 6.16 fault queue queue[1:0] number of consecutive out of limit conditions 10 0 0 1 (disabled) 01 2 10 3 1 1 4 (default) table 6.17 conversion rate conv[1:0] conversion rate 10 00 1 / sec 01 2 / sec 1 0 4 / sec (default) 1 1 continuous table 6.18 interrupt status register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 23h r-c interrupt status register - tcrit gpio fan high low fault 00h
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 50 smsc emc2103 datasheet the interrupt status register reports the operating condition of the emc2103. if any of the bits are set to a logic ?1? (other than hws) then the alert pin will be asserted low if the corresponding channel is enabled. reading from the status register clears a ll status bits if the error conditions is removed. if there are no set status bits, then the alert pin will be released. the bits that cause the alert pin to be asserted can be masked based on the channel they are associated with unless stated otherwise. bit 5 - tcrit - this bit is set to ?1? if any bit in the tcrit status register is set. this bit is automatically cleared when the tcrit status register is read and the bits are cleared. bit 4 - gpio (emc2103-2 only) - this bit is set to ?1? if any bit in the gpio stat us register is set. this bit is automatically cleared when the gpio status register is read. bit 3 - fan - this bit is set to ?1? if any bit in the fan status register is set. this bit is automatically cleared when the fan status register is read and the bits are cleared. bit 2 - high - this bit is set to ?1? if any bit in the high status register is set. this bit is automatically cleared when the high status register is read and the bits are cleared. bit 1- low - this bit is set to ?1? if any bit in the low status register is set. this bit is automatically cleared when the low status register is read and the bits are cleared. bit 0 - fault - this bit is set to ?1? if any bit in t he diode fault register is set. this bit is automatically cleared when the diode fault register is read and the bits are cleared. 6.13 error status registers the error status registers report the specific error condition for all measurement channels with limits. if any bit is set in the high, low, or diode fault st atus register, the corresponding high, low, or fault bit is set in the interrupt status register. reading the interrupt status register does not clea r the error status bit. reading from any error status register that has bits set will clear the register and the corresponding bit in the interrupt status register if the error condition has been removed. if the error condition is pe rsistent, reading the error status registers will have no affect. 6.13.1 tcrit status register the tcrit status register stores the event that c aused the sys_shdn pin to be asserted. each of the temperature channels must be associated with the sys_shdn pin before they can be set (see section 6.9 ). once the sys_shdn# pin is asserted, it will be released when the temperature drops below the threshold level however the individua l status bit will not be cleared until read. table 6.19 error status register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 1fh r-c tcrit status hws ext3 _tcr it ext2 _tcr it ext1 _tcr it int_t crit 00h 24h r-c high status - - - - ext3 _hi ext2 _hi ext1 _hi int_ hi 00h 25h r-c low status - - -- - ext3 _lo ext2 _lo ext1 _lo int_l o 00h 26h r-c diode fault - - - - ext3 _flt ext2 _flt ext1 _flt - 00h
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 51 revision 0.85 (01-29-08) datasheet 6.14 fan status register the fan status register contains the stat us bits associated with each fan driver. bit 7 - watch - this bit is asserted ?1? if the host has not programmed the fan driver within four (4) seconds after power up (i.e. the watchdog timer has timed out. see section 5.9 . bit 5 - drive_fail - indicates that the rpm based fan speed control algorithm cannot drive the fan to the desired target setting at maximum drive. this bit can be masked from asserting the alert pin. ? ?0? - the rpm based fan speed control algorithm can drive fan to the desired target setting. ? ?1? - the rpm based fan speed control algorithm c annot drive fan to the desired target setting at maximum drive. bit 1- fan_spin - this bit is asserted ?1? if the spin up routine for the fan cannot detect a valid tachometer reading within its maximum time window. this bit can be masked from asserting the alert pin. bit 0 - fan_stall - this bit is asserted ?1? if the tachometer measurement on the fan detects a stalled fan. this bit can be masked from asserting the alert pin. 6.15 interrupt enable register the interrupt enable register controls the masking for each temperature channel. when a channel is masked, it will not cause the alert pin to be asserted when an error condition is detected. bit 3 - ext3_int_en (emc2103-2 only) - allows the external diode 3 to assert the alert pin. ? ?0? (default) - the alert pin will not be asserted for any error condition associated with external diode 3 channel. ? ?1? - the alert pin will be asserted for an error condition associated with external diode 3 channel. bit 2 - ext2_int_en (emc2103-2 only) - allows the external diode 2 to assert the alert pin. ? ?0? (default) - the alert pin will not be asserted for any error condition associated with external diode 2 channel. ? ?1? - the alert pin will be asserted for an error condition associated with external diode 2 channel. bit 1 - ext1_int_en - allows the external diode 1 to assert the alert pin. ? ?0? (default) - the alert pin will not be asserted for any error condition associated with external diode 1 channel. table 6.20 fan status register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 27h r-c fan status register watch - drive _fail --- fan_ spin fan_ stall 00h table 6.21 interrupt enable register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 28 r/w interrupt enable -- -- ext3_i nt_en ext2_i nt_en ext1_i nt_en int_in t_en 00h
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 52 smsc emc2103 datasheet ? ?1? - the alert pin will be asserted for an error condition associated with external diode 1 channel. bit 0 - int_int_en - allows the in ternal diode to assert the alert pin. ? ?0? (default) - the alert pin will not be asserted for any error condition associated with the internal diode. ? ?1? - the alert pin will be asserted for an error condition associated with the internal diode. 6.16 fan interrupt enable register the fan interrupt enable register controls the ma sking for errors generated by the fan driver. when a channel is masked, it will not cause the alert pin to be asserted when an error condition is detected. bit 1 - spin_int_en - allows the fan_spin bit to assert the alert pin. ? ?0? (default) - the fan_spin bit will not assert the alert pin though it will st ill update the status register normally. ? ?1? - the fan_spin bit will assert the alert pin. bit 0 - stall_int_en - allows the fan_stall bit or drive_fail bit to assert the alert pin. ? ?0? (default) - the fan_stall bit or drive_fail bit will not assert the alert pin though will still update the status register normally. ? ?1? - the fan_stall bit will assert the alert pin. 6.17 pwm configuration register the pwm config register controls the outp ut type and polarity of the pwm output. bit 4 - pwm_ot - determines the output type for the pwm pin. ? ?0? (default) - the pwm pin is c onfigured as an open drain output. ? ?1? - the pwm pin is configured as a push-pull output. table 6.22 fan interrupt enable register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 29 r/w fan interrupt enable ------ spin_ int_en stall_ int_en 00h table 6.23 pwm configuration register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 2ah r/w pwm config --- pwm_ ot --- pola rity 00h
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 53 revision 0.85 (01-29-08) datasheet bit 0 - polarity1 - determines the polarity of pwm1 (if enabled). ? ?0? (default) - the polarity of the pwm driver is normal. a drive setting of 00h will cause the output to be set at 0% duty cycle and a drive setting of ffh will cause th e output to be set at 100% duty cycle. ? ?1? - the polarity of the pwm driver is inverted. a drive setting of 00h will cause the output to be set at 100% duty cycle and a drive setting of ffh will cause the ou tput to be set at 0% duty cycle. 6.18 pwm base frequency register the pwm base frequency register contro ls base frequency of the pwm output. bits 1-0 - pwm_base[1:0] - determines the base frequency of the pwm driver (pwm). 6.19 limit registers table 6.24 pwm base frequency register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 2bh r/w pwm base frequency ---- - - pwm_base[1:0 ] 03h table 6.25 pwm_basex[1:0] it decode pwm_base[1:0] base frequency 10 0 0 26.00khz 0 1 19.531khz 1 0 4,882hz 1 1 2,441hz (default) table 6.26 limit registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 30h r/w external diode 1 high limit sign 64 32 16 8 4 2 1 55h (+85c) 31h ** r/w external diode 2 high limit ** sign 64 32 16 8 4 2 1 55h (+85c) 32h ** r/w external diode 3 high limit ** sign 64 32 16 8 4 2 1 55h (+85c) 34h r/w internal diode high limit sign 64 32 16 8 4 2 1 55h (+85c) 38h r/w external diode 1 low limit sign 64 32 16 8 4 2 1 00h (0c)
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 54 smsc emc2103 datasheet the emc2103 contains high limits for all temperat ure channels. if any meas urement meets or exceeds the high limit then the appropriate status bit is set and the alert pin is asserted (if enabled). additionally, the emc2103 contains low limits for all temperature channels. if the temperature channel drops below the low limit, then the appropr iate status bit is set and the alert pin is asserted (if enabled). all limit registers are software locked. 6.20 fan setting registers the fan setting register always displays the current setting of the fan driver. reading from the register will report the current fan speed setting of the fan driver regardless of the operating mode. therefore it is possible that read ing from this register will not report data that was previously written into this register. while the rpm based fan speed control algorithm or the look up table are active (or both), then the register is read only. writing to the regist er will have no affect and the data will not be stored. if both the rpm based fan contro l algorithm and the look up tabl e are disabled, then the register will be set with the previous value that was used. the re gister is read / write and writing to this register will affect the fan speed. the contents of the register represent the weighting of each bit in determining the final duty cycle. the output drive for a pwm output is given by equation [1] . 6.21 pwm divide register 39h ** r/w external diode 2 low limit ** sign 64 32 16 8 4 2 1 00h (0c) 3ah ** r/w external diode 3 low limit ** sign 64 32 16 8 4 2 1 00h (0c) 3ch r/w internal diode low limit sign 64 32 16 8 4 2 1 00h (0c) table 6.27 fan driver setting register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 40h r/w fan setting 128 64 32 16 8 4 2 1 00h [1] table 6.28 pwm divide register addrr/wregisterb7b6b5b4b3b2b1b0default 41h r/w pwm divide 128 64 32 16 8 4 2 1 01h table 6.26 limit registers (continued) addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default drive value 255 -------------------- - ?? ?? 100% =
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 55 revision 0.85 (01-29-08) datasheet the pwm divide register determines the final frequen cy of the pwm driver. the driver base frequency is divided by the value of the pwm divide register to determine th e final frequency. the duty cycle settings are not affected by these settings, only the final frequency of the pwm driver. a value of 00h will be decoded as 01h. the final pwm frequency is derived as the base fr equency divided by the value of this register as shown in equation [2] . 6.22 fan configuration 1 register the fan configuration 1 register controls the general operation of the rpm based fan speed control algorithm used on the pwm pin. bit 7 - en_algo - enables the rpm based fan spe ed control algorithm. based on the setting of the rpm / pwm bit, this bit is auto matically set or cleared when the lut_lock bit is set (see section 6.32 ). ? ?0? - (default) the control circuitry is disabled and the fan driver output is determined by the fan driver setting register. ? ?1? - the control circuitry is enabled and the fa n driver output will be automatically updated to maintain the programmed fan speed as indicated by the tach target register. bits 6- 5 - range[1:0] - adjusts the range of re ported and programmed tac hometer reading values. the range bits determine the weighting of all tach values (including the valid tach count, tach target, and tach reading) as shown in ta b l e 6 . 3 0 . bits 4-3 - edges[1:0] - determine s the minimum number of edges t hat must be detected on the tach signal to determine a single rotation. a typical fan measured 5 edges (for a 2-pole fan). for more accurate tachometer measurement, the minimu m number of edges measured may be increased. increasing the number of edges m easured with respect to the number of poles of the fan will cause the tach reading registers to indicate a fan speed that is higher or lowe r than the actual speed. in order for the fsc algorithm to operate correctly, the tach target must be updated by the user to accommodate this shift. the effective tach multiplier shown in ta b l e 6 . 3 1 is used as a direct multiplier [2] table 6.29 fan configuration 1 register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 42h r/w fan configuration 1 en_ algo range[1:0] edges[1:0] update[2:0] 2bh table 6.30 range decode range[1:0] reported minimum rpm tach count multiplier 10 005001 0 1 1000 (default) 2 1 0 2000 4 1 1 4000 8 f pwm pwm base freqeuncy pwm divide setting -------------------------------------------------------------- - =
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 56 smsc emc2103 datasheet term that is applied to the actual rpm to achieve the reported rpm. it should only be applied if the number of edges measured does not match the numbe r of edges expected based on the number of poles of the fan (which is fixed for any given fan). contact smsc for recommended settings when us ing fans with more or less than 2 poles. bit 2-0 - update - determines the base time be tween fan driver updates. the update time, along with the fan step register, is used to control the ra mp rate of the drive response to provide a cleaner transition of the actual fan operation as the de sired fan speed changes. the update time is set as shown in ta b l e 6 . 3 2 . 6.23 fan configuration 2 register table 6.31 minimum edges for fan rotation edges[1:0] minimum tach edges number of fan poles effective tach multiplier (based on 2 pole fans) 10 0 0 3 1 pole 0.5 0 1 5 2 poles (default) 1 1 0 7 3 poles 1.5 1 1 9 4 poles 2 table 6.32 update time update[2:0] update time 21 0 00 0 100ms 00 1 200ms 01 0 300ms 0 1 1 400ms (default) 10 0 500ms 10 1 800ms 1 1 0 1200ms 1 1 1 1600ms table 6.33 fan configuration 2 register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 43h r/w fan configuration 2 - en_ rrc glitch _en der_opt [1:0] err_rng:0] - 38h
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 57 revision 0.85 (01-29-08) datasheet the fan configuration 2 register controls the tac hometer measurement and ad vanced features of the rpm based fan speed control algorithm. bit 6 - en_rrc - enables ramp rate control when the fan driver is operated in the direct setting mode or the direct setting with lut mode. ? ?0? (default) - ramp rate control is disabled. w hen the fan driver is operating in direct setting mode or direct setting with lut mode, the pwm setting will instantly transition to the next programmed setting. ? ?1? - ramp rate control is enabled. when the fan driver is operating in direct setting mode or direct setting with lut mode, the pwm se tting will follow the ramp rate controls as determined by the fan step and update time settings. the maximum pwm step is capped at the fan step setting and is updated based on the update time as given by table 6.32 . bit 5 - glitch_en - disables the low pass glitch filt er that removes high frequency noise injected on the tach pin. ? ?0? - the glitch filter is disabled. ? ?1? (default) - the glit ch filter is enabled. bits 4 - 3 - der_opt[1:0] - control some of the advanced options that affect the derivative portion of the rpm based fan speed control algorithm as shown in ta b l e 6 . 3 4 . note that the default derivative options disable the ramp rate control maximum step settings. to take advantage of the full ramp rate control, limit derivative options to the disabled or basic derivative settings. bit 2 - 1 - err_rng[1:0] - control some of the adv anced options that affect the error window. when the measured fan speed is within the programmed error window around the target speed, then the fan drive setting is not updated. the algorithm will continue to monitor the fan speed and calculate necessary drive setting changes based on t he error, however these changes are ignored. table 6.34 deri vative options der_opt[1:0] operation 10 0 0 no derivative terms used 01 basic derivative. the derivative of the error from the current drive setting and the target is added to the iterative fan driv e setting (in addition to proportional and integral terms) 10 step derivative. the derivative of the error from the current drive setting and the target is added to the iterative fan dr ive setting and is not capped by the maximum fan step register setting. 11 both the basic derivative and the step derivative are used effectively causing the derivative term to have double the effect of the derivative term (default).
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 58 smsc emc2103 datasheet the fan configuration 2 register is software locked. 6.24 gain register the gain register stores the gain terms used by the proportional and integral portions of the rpm based fan speed control algorithm. these terms will affect the fsc closed loop acquisition, overshoot, and settling as would be expected in a classic pid system. 6.25 fan spin up configuration register the fan spin up configuration register co ntrols the settings of spin up routine. table 6.35 error range options err_rng[1:0] operation 10 0 0 0 rpm (default) 0 1 50 rpm 1 0 100 rpm 1 1 200 rpm table 6.36 gain register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 45h r/w gain register - - gaind[ 1:0] gaini[1:0] gainp[1:0] 2ah table 6.37 gain decode gaind or gainp or gaini [1:0] respective gain factor 10 00 1x 01 2x 1 0 4x (default) 11 8x table 6.38 fan spin up configuration register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 46h r/w fan spin up configuration drive_fail _cnt [1:0] nok ick spin_lvl[2:0] spinup_time [1:0] 19h
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 59 revision 0.85 (01-29-08) datasheet bit 7 - 6 - drive_fail_cnt[1:0] - determines ho w many update cycles are used for the drive fail detection function as shown in ta b l e 6 . 3 9 . this circuitry determines whether the fan can be driven to the desired tach target. bit 5 - nokick - determines if the spin up routine will drive the fan to 100% duty cycle for 1/4 of the programmed spin up time before dr iving it at the programmed level. ? ?0? (default) - the spin up routine will drive the pwm to 100% for 1/4 of the programmed spin up time before reverting to the programmed spin level. ? ?1? - the spin up routine will not drive the pwm to 100%. it will set the drive at the programmed spin level for the entire duration of the programmed spin up time. bits 4 - 2 - spin_lvl[2:0] - determines the final dr ive level that is used by the spin up routine as shown in ta b l e 6 . 4 0 . bit 1 -0 - spinup_time[1:0] - determines the maximu m spin time that the spin up routine will run for (see section 5.7 ). if a valid tachometer measurement is not detected before the spin time has elapsed, then an interrupt will be generated. w hen the rpm based fan speed control algorithm is active, the fan driver will attempt to re-start the fan immediately after the end of the last spin up attempt. the spin time is set as shown in ta b l e 6 . 4 1 . table 6.39 drive_fail_cnt[1:0] bit decode drive_fail_cnt[1:0] number of update periods 10 00 disabled - the drive fail detection circuitry is disabled 01 16 - the drive fail detection circuitry will count for 16 update periods 10 32 - the drive fail detection circuitry will count for 32 update periods 11 64 - the drive fail detection circuitry will count for 64 update periods table 6.40 spin level spin_lvl[2:0] spin up drive level 210 0 0 0 30% 0 0 1 35% 0 1 0 40% 0 1 1 45% 1 0 0 50% 1 0 1 55% 1 1 0 60% (default) 1 1 1 65%
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 60 smsc emc2103 datasheet the fan spin up configuration register is software locked. 6.26 fan step register the fan step register, along with the update time, c ontrol the ramp rate of the fan driver response. the value of the registers represents the maximum step size each fan driver will take between update times (see section 6.22 ). all modes of operation have the options to use the fan step register (and update times) for ramp rate control based on the fan configuration 2 register settings. the fan speed control algorithm will always use the fan step register settings (but see application note below). application note: if the fan speed control algorithm is used, t he default settings in the fan configuration 2 register will cause the maximum fan step settings to be ignored. the fan step register is software locked. 6.27 fan minimum drive register the fan minimum drive register stores the minimum drive setting for the rpm based fan speed control algorithm. this register is not used if t he fsc is not active. the rpm based fan speed control algorithm will not drive the fan at a level lower t han the minimum drive unless the target tach target is set at ffh (see section 6.30 ) during normal operation, if the fan stops for any reason (including low drive), the rpm based fan speed control algorithm will attempt to restart the f an. setting the fan minimum drive registers to a table 6.41 spin time spinup_time[1:0] total spin up time 10 0 0 250 ms 0 1 500 ms (default) 1 0 1 sec 1 1 2 sec table 6.42 fan step register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 47h r/w fan max step - - 32 16 8 4 2 1 10h table 6.43 minimum fan drive register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 48h r/w fan minimum drive 128 64 32 16 8 4 2 1 66h (40%)
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 61 revision 0.85 (01-29-08) datasheet setting that will maintain fan operat ion is a useful way to avoid potent ial fan oscillations as the control circuitry attempts to drive it at a le vel that cannot support fan operation. the fan minimum drive register is software locked. 6.28 valid tach count register the valid tach count register store the maximum ta ch reading register value to indicate that the the fan is spinning properly. the value is referenced at the end of the spin up routine to determine if the fan has started op erating and decide if the device needs to retry. see equation [4] for translating the count to an rpm. if the tach reading register value exceeds the valid tach count register (indicating that the fan rpm is below the threshold set by this count), then a stalled fan is detected. in this condition, the algorithm will automatically begin its spin up routine. application note: the automatic invoking of the spin up rout ine only applies if the fan speed control algorithm is used. if the fsc is disabled, then the device will only invoke the spin up routine when the pwm setting changes from 00h. if a tach target setting is set above the valid tach count setting, then that setting will be ignored and the algorithm will use the current fan drive setting. the valid tach count register is software locked. 6.29 fan drive fail band registers the fan drive fail band registers store the num ber of tach counts used by the fan drive fail detection circuitry. this circuitry is activated when the fan drive setting high byte is at ffh. when it is enabled, the actual measured fan speed is compared against the target fan speed. this circuitry is used to indicate that the target fan speed at full drive is higher than the fan is actually capable of reaching. if the measured fan speed does not exceed the target fan speed minus the fan drive fail band register settings for a period of time longer than set by the drive_fail_cntx[1:0] bits then the drive_fail status bit will be set and an interrupt generated. table 6.44 valid tach count register addrr/wregisterb7b6b5b4b3b2b1b0default 49h r/w valid tach count 4096 2048 1024 512 256 128 64 32 f5h table 6.45 fan drive fail band registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 4ah r/w fan drive fail band low byte 16 8 4 2 1 - - - 00h 4bh r/w fan drive fail band high byte 4096 2048 1024 512 256 128 64 32 00h
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 62 smsc emc2103 datasheet 6.30 tach target register the tach target register holds the target tachomet er value that is maintained by the rpm based fan speed control algorithm. the value in the tach target register will always re flect the current tach target value. if the look up table is active and configured to operate in rpm mode, then this register will be read only. writing to this register will have no affe ct and the data will not be stored. if the algorithm is enabled then se tting the tach target register to ffh will disable the fan driver (set the pwm duty cycle to 0%). setting the tach target to any othe r value (from a sett ing of ffh) will cause the algorithm to invoke the spin up ro utine after which it will function normally. 6.31 tach reading register the tach reading register contents describe the curr ent tachometer reading for the fan. by default, the data represents the fan speed as the number of 32khz clock periods that occur for a single revolution of the fan. equation [3] shows the detailed conversion from tach measurement (count) to rpm while equation [4] shows the simplified translation of tach readin g register count to rpm assuming a 2-pole fan, measuring 5 edges, with a frequency of 32.768khz. see appendix b for a table enumerating the rpm to tach conversion for the default settings. table 6.46 tach target register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 4ch r/w fan tach target low byte 168421 - - - f8h 4dh r/w tach target 4096 2048 1024 512 256 128 64 32 ffh table 6.47 tach reading register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 4eh r fan tach 4096 2048 1024 512 256 128 64 32 ffh 4fh r fan tach low byte 168421 - - - f8h
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 63 revision 0.85 (01-29-08) datasheet 6.32 look up table configuration register the look up table configuration register controls the setup information for the temperature to fan drive look up table. bit 7 - use_dts_f1 - this bit determines whether the pushed temperature 1 register is using dts data. ? ?0? (default) - the pushed temper ature 1 register is not using dts data. the contents of the pushed temperature 1 registers is standard temperature data. ? ?1? - the pushed temperature 1 register is loaded with dts data. the contents of this register is automatically subtracted from a fixed value of 100c before being compared to the look up table threshold levels. bit 6 - use_dts_f2 - this bit determines whether the pushed temperature 2 register is using dts data. ? ?0? (default) - the pushed temper ature 2 register is not using dts data. the contents of this register is standard 2?s co mplement temperature data. ? ?1? - the pushed temperature 2 register is loaded with dts data. the contents of this register is automatically subtracted from a fixed value of 100c before being compared to the look up table threshold levels. bit 5 - lut_lock - this bit locks updating the look up table entries and determines whether the look up table is being used. ? ?0? (default) - the look up table entries can be updated normally. the look up table will not be used while the look up table entries are unlocked. during this condition, the pwm output will not change states regardless of temper ature or tachometer variation. ? ?1? - the look up table entries are locked and canno t be updated. the look up table is fully active and will be used based on the loaded values. th e pwm output will be updated depending on the temperature and / or tach variations. application note: when the lut_lock bit is set at a logic ?0?, the pwm drive setting will be set at whatever value was last used by the rpm based fan spe ed control algorithm or the look up table. where: [3] poles = number of poles of the fan (typically 2) n = number of edges measured (typically 5) m = the multiplier defined by the range bits [4] count = tach reading register value (in decimal) table 6.48 look up table configuration register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 50h r/w lut configuration use_d ts_f1 use_d ts_f2 lut_l ock rpm / pwm - temp3 _cfg - temp4 _cfg 00h rpm 1 poles () -------------------- n 1 ? () count 1 m ---- - --------------------------------- - 1,966,080 = rpm 3,932,160 m count -------------------------------------- =
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 64 smsc emc2103 datasheet bit 4 - rpm / pwm - this bit selects the data format for the lut drive settings. ? ?0? (default) - the look up table drive settings are rpm tach count values for use by the rpm based fan speed control algorithm. the look up table drive settings should be loaded highest value to lowest value (to coincide with the inversion between tach counts and actual rpm). ? ?1? - the look up table drive settings are pwm dut y cycle values and are used directly. the drive settings should be loaded lowest value to highest value. bit 2 - temp3_cfg - determine the temperature channel that is used for the temperature 3 inputs to the look up table. if the external diode 3 channel is not enabled, then the temperature 3 inputs are not used by the look up table. ? ?0? (default) - the external diode 3 channel is used by the fan look up table (if enabled). ? ?1? - the data written into the pushed temperature 1 register is used by the fan look up table. bit 0 - temp4_cfg - determine the temperature channel that is used for the temperature 4 inputs to the look up table. ? ?0? (default) - the internal channel is used by the fan look up table. ? ?1? - the data written into the pushed temperature 2 register is used by the fan look up table. 6.33 look up table registers table 6.49 look up table registers addr r/w register rpm / pwmb7 b6 b5 b4b3b2b1b0default 51h r/w lut drive setting 1 ?0? 4096 2048 1024 512 256 128 64 32 fbh ?1? 128 64 32 16 8 4 2 1 52h r/w lut ext diode 1 setting 1 x - 64 32 16 8 4 2 1 7fh (127c) 53h r/w lut ext diode 2 setting 1 x - 64 32 16 8 4 2 1 7fh (127c) 54h r/w lut temp 3 setting 1 x - 64 32 16 8 4 2 1 7fh (127c) 55h r/w lut temp 4 setting 1 x - 64 32 16 8 4 2 1 7fh (127c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74h r/w lut drive setting 8 ?0? 4096 2048 1024 512 256 128 64 32 92h ?1? 128 64 32 16 8 4 2 1 75h r/w lut ext diode 1 setting 8 x - 64 32 16 8 4 2 1 7fh (127c) 76h r/w lut ext diode 2 setting 8 x - 64 32 16 8 4 2 1 7fh (127c) 77h r/w lut temp 3 setting 8 x - 64 32 16 8 4 2 1 7fh (127c)
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 65 revision 0.85 (01-29-08) datasheet the look up table registers hold the 40 entries of th e look up table that cont rols the drive of the pwm. as the temperature channels are updated, th e measured value for each channel is compared against the respective entries in the look up tabl e and the associated drive setting is loaded into an internal shadow register and stored. the bit weighting for temperature inputs represents c and is compared against the measured data. note that the lut entry does not include a sign bi t. the look up table does not support negative temperature values and the msbit should not be set for a temperature input. each temperature channel threshold shares th e same hysteresis value. when the measured temperature for any of the channel s meets or exceeds the programme d threshold, the drive setting associated with that threshold is used. the tem perature must drop below the threshold minus the hysteresis value before the drive setti ng will be set to the previous value. if the rpm based fan speed control algorithm is used, the tach target is updated after every conversion. it is always set to the minimum tach tar get that is stored by the look up table. the pwm duty cycle is updated based on the rpm base d fan speed control algorithm configuration settings. if the rpm based fan speed control algorithm is no t used, then the pwm duty cycle is updated after every conversion. it is set to the maximum duty cycle that is stored by the look up table. 6.34 gpio direction register (emc2103-2 only) the gpio direction register controls the direction of gpios 1 and 2. bit 1 - gpio2_dir - determines the direction of gpio2. ? ?0? (default) - gpio2 is configured as an input. ? ?1? - gpio1 is configured as an output. bit 0 - gpio2_dir - determines the direction of gpio1. ? ?0? (default) - gpio1 is configured as an input. ? ?1? - gpio1 is configured as an output. 78h r/w lut temp 4 setting 8 x - 64 32 16 8 4 2 1 7fh (127c) 79h r/w lut temp hysteresis x - - -168421 0ah table 6.50 gpio direction register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default e1h r/w gpio direction 1 -- gpio 2_dir gpio 1_dir 00h table 6.49 look up table registers (continued) addr r/w register rpm / pwmb7 b6 b5 b4b3b2b1b0default
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 66 smsc emc2103 datasheet 6.35 gpio output configurat ion register (emc2103-2 only) the gpio output config uration register controls the out put pin type of each gpio pin. bit 1 - gpio2_ot - determines the output type for gpio2. ? ?0? (default) - gpio2 is configured as an open drain output (if enabled as an output). ? ?1? - gpio2 is configured as a push-pull output (if enabled as an output). bit 0 - gpio1_ot - determines the output type for gpio1. ? ?0? (default) - gpio1 is configured as an open drain output (if enabled as an output). ? ?1? - gpio1 is configured as a push-pull output (if enabled as an output). 6.36 gpio input regi ster (emc2103-2 only) the gpio input register indicates the state of the corresponding gpio pin. when a gpio is configured as an input, any change of state will as sert the alert# pin (unless gpio interrupts are masked, see section 6.15 ). bit 1 - gpio2_in - indicates the pin state of t he gpio2 pin regardless of the pin functionality. bit 0 - gpio1_in - indicates the pin state of t he gpio1 pin regardless of the pin functionality. 6.37 gpio output re gister (emc2103-2 only) the gpio output register contro ls the state of the corresponding pins when they are configured as outputs. if the output is configured as an open-drain output, then it requires a pull-up resistor to vdd. setting the corresponding bit to a ?1? will act to disable the output allowing the pull-up resistor to pull the output high. setting the corresponding bit to a ?0? will enable the output and drive the pin to a logical ?0? state. table 6.51 gpio output configuration register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default e2 r/w gpio output config - gpio 2_ot gpio 1_ot 00h table 6.52 gpio input register addrr/wregisterb7b6b5b4b3b2 b1 b0default e3h r gpio input - - gpio 2_in gpio 1_in 00h table 6.53 gpio output register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default e4h r/w gpio output 1 -- gpio2 _out gpio1 _out 00h
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 67 revision 0.85 (01-29-08) datasheet if the output is configured as a push-pull output, then output pin wil l immediately be driven to match the corresponding bit setting. bit 1 - gpio2_out - controls the pin state of the gp io2 pin when it is configured as a gpio output. bit 0 - gpio1_out - controls the pin state of the gp io1 pin when it is configured as a gpio output. 6.38 gpio interrupt enab le register (emc2103-2 only) the gpio interrupt enable register en ables the gpios to assert the alert pin when they change state. when the gpio pins are configured as outputs, then these bits are ignored. bit 1 - gpio2_int_en - allows the alert pin to be asserted when the gpio2 pin changes state (when configured as an input). ? ?0? (default) - the alert pin will not be asserted when the gpio2 pin changes state (when configured as an input). ? ?1? - the alert pin will be asserted when the gpio2 pin changes state (when configured as an input) bit 0 - gpio1_int_en - allows the alert pin to be asserted when the gpio1 pin changes state (when configured as an input). ? ?0? (default) - the alert pin will not be asserted when the gpio1 pin changes state (when configured as an input). ? ?1? - the alert pin will be asserted when the gpio1 pin changes state (when configured as an input) 6.39 gpio status register (emc2103-2 only) the gpio status register indicates which gpio has changed states to cause the alert pin to be asserted. this register is cleared when it is read . the bits in this register are set whenever the corresponding gpio changes states regardless if the alert pins are asserted. once a bit is set, it will remain set until read. if any bit in this register is set, then the gpio status bit will be set. bit 1 - gpio2_sts - indicates that the gpio2 pin has changed states from a ?0? to a ?1? or a ?1? to a ?0? (when configured as a gpio input). bit 0 - gpio1_sts - indicates that the gpio1 pin has changed states from a ?0? to a ?1? or a ?1? to a ?0? (when configured as a gpio input). table 6.54 gpio interrupt enable register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default e5h r/w gpio interrupt enable -- gpio2_ int_en gpio1_ int_en 00h table 6.55 gpio status register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default e6h r-c gpio status -- gpio2_ sts gpio1_ sts 00h
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 68 smsc emc2103 datasheet 6.40 software lock register the software lock register controls the software locking of critical re gisters. this register is software locked. bit 0 - lock - this bit acts on all registers that ar e designated swl. when this bit is set, the locked registers become read on ly and cannot be updated. ? ?0? (default) - all swl registers can be updated normally. ? ?1? - all swl registers cannot be updated and a hard-reset is required to unlock them. 6.41 product features register the product features register indicates wh ich pin selected functionality is enabled. table 6.56 software lock addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default efh r/w software lock -------lock00h table 6.57 product features register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default fch r product features - - - - - shdn_sel[2:0] 00h table 6.58 shdn_sel[2:0] encoding shdn_sel[2:0] diode mode other features 210 0 0 0 external diode 1 simple mode - beta compensation disabled, rec disabled - recommended for amd cpu diodes none 0 0 1 external diode 1 diode mode - beta compensation disabled, rec enabled none 0 1 0 external diode 1 transistor mode - beta compensation enabled, rec enabled - - recommended for intel 45nm and 65mn cpu diodes none 0 1 1 internal diode transistor mode - beta compensation enabled, rec enabled none 1 0 0 external diode 2 transistor mode - beta compensation enabled, rec enabled (emc2103-2 only) external diode 1 diode mode (emc2103-1 only) none 1 0 1 external diode 1 transistor mode - beta compensation enabled, rec enabled none
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 69 revision 0.85 (01-29-08) datasheet 6.42 product id register the product id register contains a unique 8-bit word that identifies the product. 6.43 manufacturer id register the manufacturer id register contains an 8-bit word that identifies smsc. 6.44 revision register the revision register contains an 8-bit word that identifies the die revision. ? ?0? - the lower 3 bits are writable for a range of 1.0053 to 1.0146 ? ?1? - the lower 4 bits are writable for a range of 1.0053 to 1.0253 dbh - idcf trim register - sets the default value for the idcf1 register. table 6.59 product id register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default fdh r product id register (emc2103-1) 00100100 24h product id register (emc2103-2) 00100110 26h table 6.60 manufacturer id register addr r/w register b7b6b5b4b3b2b1b0default feh r manufacturer id 01011101 5dh table 6.61 revision register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default ffh r revision 0 0 0 0 0 0 0 1 01h
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 70 smsc emc2103 datasheet chapter 7 package drawing 7.1 emc2103-1 pack age information figure 7.1 preliminary 12 pin qfn 4mm x 4mm package dimensions
smsc emc2103 71 revision 0.85 (01-29-08) datasheet rpm-based fan controller with hw thermal shutdown datasheet figure 7.2 preliminary 12 pin qf n 4mm x 4mm package drawing
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 72 smsc emc2103 datasheet figure 7.3 recommended pcb footprint 12-pin qfn 4mm x 4mm
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 73 revision 0.85 (01-29-08) datasheet 7.2 emc2103-2 pack age information figure 7.4 preliminary 16 pin qfn 4mm x 4mm package dimensions
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 74 smsc emc2103 datasheet figure 7.5 preliminary 16 pin qfn 4mm x 4mm package drawing
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 75 revision 0.85 (01-29-08) datasheet figure 7.6 recommended pcb footprint 16-pin qfn 4mm x 4mm
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 76 smsc emc2103 datasheet appendix a look up table operation the emc2103 uses a look-up table to apply a user-programmable fan control profile based on measured temperature to the fan dr iver. in this look-up table, each temperature channel is allowed to control the fan drive output independently (or jointly) by programming up to eight pairs of temperature and drive setting entries. the user programs the look-up table based on the desired operation. if the rpm based fan speed control algorithm is to be used (see section 5.5 ), then the user must program an rpm target for each temperature setting of interest. alternately, if the rpm based fan speed control algorithm is not to be used, then the user must program a drive sett ing for each temperatur e setting of interest. if the measured temperature on the external diode c hannel meets or exceeds any of the temperature thresholds for any of the channels, the fan output will be automatically set to the desired setting corresponding to the exceeded temperature. in ca ses where multiple temperature channel thresholds are exceeded, the highest fan driv e setting will take precedence. when the measured temperat ure drops to a point below a lower threshold minus the hysteresis value, the fan output will be set to t he corresponding lower set point. the following sections show examples of how the look up table is used and configured. each look up table example uses the fan 1 look up table registers configured as shown in table a.1 . a.1 example #1 this example does not use the rpm based fan speed control algorithm. instead, the look up table is configured to directly set a pwm setting based on the temperature of four of its measured inputs. the configuration is set as shown in ta b l e a . 2 . once configured, the look up table is loaded as shown in ta b l e a . 3 . ta b l e a . 3 shows three temperature configurations using the settings in ta b l e a . 3 and the final pwm output drive setting that the look up table will select. table a.1 look up table format step temp 1 temp 2 temp 3 temp 4 lut drive 1 lut temp 1 setting 1 (52h) lut temp 2 setting 1 (53h) lut temp 3 setting 1 (54h) lut temp 4 setting 1 (55h) lut drive setting 1 (51h) 2 lut temp 1 setting 2 (57h) lut temp 2 setting 2 (58h) lut temp 3 setting 2 (59h) lut temp 4 setting 2 (5ah) lut drive setting 2 (56h) 3 lut temp 1 setting 3 (5ch) lut temp 2 setting 3 (5dh) lut temp 3 setting 3 (5eh) lut temp 4 setting 3 (5fh) lut drive setting 3 (5bh) 4 lut temp 1 setting 4 (61h) lut temp 2 setting 4 (62h) lut temp 3 setting 4 (63h) lut temp 4 setting 4 (64h) lut drive setting 4 (60h) 5 lut temp 1 setting 5 (66h) lut temp 2 setting 5 (67h) lut temp 3 setting 5 (68h) lut temp 4 setting 5 (69h) lut drive setting 5 (65h) 6 lut temp 1 setting 6 (6bh) lut temp 2 setting 6 (6ch) lut temp 3 setting 6 (6dh) lut temp 4 setting 6 (6eh) lut drive setting 6 (6ah) 7 lut temp 1 setting 7 (70h) lut temp 2 setting 7 (71h) lut temp 3 setting 7 (72h) lut temp 4 setting 7 (73h) lut drive setting 7 (6fh) 8 lut temp 1 setting 8 (75h) lut temp 2 setting 8 (76h) lut temp 3 setting 8 (77h) lut temp 4 setting 8 (78h) lut drive setting 8 (74h)
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 77 revision 0.85 (01-29-08) datasheet note: the values shown in table a.3 are example settings. all the cells in the look-up table are programmable via smbus. table a.2 look up table example #1 configuration addr register b7 b6 b5 b4 b3 b2 b1 b0 setting 50h lut 1 configuration use_d ts_f1 use_d ts_f2 lut_l ock rpm / pwm - temp3 _cfg - temp4 _cfg c0h 00110000 table a.3 fan speed control table example #1 fan speed step # external diode 1 temperature (cpu) external diode 2 temperature (gpu) external diode 3 temperature (skin) internal diode temperature (ambient) pwm settings 135 o c60 o c30 o c40 o c0% 240 o c70 o c35 o c45 o c 30% 350 o c75 o c40 o c50 o c 40% 460 o c80 o c45 o c55 o c 50% 570 o c85 o c50 o c60 o c 60% 680 o c90 o c55 o c65 o c 70% 790 o c95 o c60 o c70 o c 80% 8 100 o c100 o c65 o c75 o c 100% table a.4 fan speed determination for example #1 (using settings in ta b l e a . 3 ) external diode 1 temperature (cpu) external diode 2 temperature (gpu) external diode 3 temperature (skin) internal diode temperature (ambient) pwm result example 1: 82c 82c 48c 58c 70% (cpu temp requires highest drive) example 2: 82c 97c 62c 58c 80% (gpu and skin require highest drive) example 3: 82c 97c 62c 75c 100% (internal temp requires highest drive)
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 78 smsc emc2103 datasheet a.2 example #2 this example uses the rpm based fan speed control algorithm. the spin level (used by the spin up routine) should be changed to 50% drive for a total spin time of 1 second. for all other rpm configuration settings, the default conditions are used. for control inputs, it uses the external diode 1 channel normally, the external diode 2 channel normally, and both pushed temperature registers in dts format. the configuration is set as shown in table a.5 while table a.6 shows how the table is loaded. note that when using dts data, the use_dts_f1 and / or use_dts_f2 bits should be set. the pushed temperature registers are loaded with the no rmal dts values as received by the processor. when the dts value is used by the look up table, th e value that is stored in the pushed temperature register is subtracted fr om a fixed temperature of 100c. this resultant value is then compared against the look up table thresholds normally. when programming the look up table, it is necessary to take this translation into account or else incorrect settin gs may be selected. table a.5 look up table example #2 configuration addr register b7 b6 b5 b4 b3 b2 b1 b0 setting 42h fan 1 configuration 1 en_ algo range[1:0] edges[1:0] update[2:0] cbh 1 1 001011 46h fan 1 spin up configuration drive_fail_cnt1 [1:0] nokick 1 spin_lvl[2:0] spinup_time [1:0] 0ah 0 0 001010 50h lut 1 configuration use_dt s_f1 use_d ts_f2 lut_lo ck rpm / pwm - temp3 _cfg temp 3_cfg e5h 1 1 100101 table a.6 fan speed control table example #2 fan speed step # external diode 1 temperature (cpu) external diode 2 temperature (gpu) pushed temperature setting (dts1) pushed temperature setting (dts2) tach target 135 o c65 o c50 o c40 o c 3dh (1007 rpm) 240 o c75 o c55 o c45 o c 1eh (2048 rpm) 350 o c85 o c60 o c50 o c 14h (3072 rpm) 460 o c90 o c65 o c55 o c 0fh (4096 rpm) 570 o c95 o c70 o c60 o c 0ch (5120 rpm) 680 o c 100 o c75 o c65 o c 0ah (6144 rpm)
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 79 revision 0.85 (01-29-08) datasheet note: the values shown in table a.6 are example settings. all the cells in the look-up table are programmable via smbus. 790 o c 105 o c80 o c80 o c 09h (6826 rpm) 8100 o c110 o c85 o c100 o c 08h (7680 rpm) table a.7 fan speed determination for example #2 (using settings in ta b l e a . 6 ) external diode 1 temperature (cpu) external diode 2 temperature (gpu) pushed temperature (dts1) pushed temperature (dts2) pwm result example 1: 75c 75c 35c (translated as 65c) 50c (translated as 50c) 0ch (5120 rpm) - cpu requires highest target example 2: 75c 90c 15c (translated as 85c) 20c (translated as 80c) 08h (7680 rpm) - dts1 requires highest target example 3: 75c 97.25c 30c (translated as 70c) 5c (translated as 95c) 09h (6826 rpm) - dts2 requires highest target table a.6 fan speed control table example #2 (continued) fan speed step # external diode 1 temperature (cpu) external diode 2 temperature (gpu) pushed temperature setting (dts1) pushed temperature setting (dts2) tach target
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 80 smsc emc2103 datasheet appendix b rpm to tachometer count look up tables b.1 1k rpm range the look up table is an example based on the a ssumption that the fan being measured has 2-poles and is measuring 5 edges using the 1k rpm range settings. the data present ed in the reading is only the high byte data and the decimal count value only represents high byte data. table b.1 tachometer count to rpm look up table (range = 1000 rpm) tach count (decimal) register reading (hex) fan speed (rpm) tach count (decimal) register reading (hex) fan speed (rpm) 0 00 disabled 4096 80 1920 32 01 245760 4128 81 1905 64 02 122880 4160 82 1890 96 03 81920 4192 83 1876 128 04 61440 4224 84 1862 160 05 49152 4256 85 1848 192 06 40960 4288 86 1834 224 07 35109 4320 87 1820 256 08 30720 4352 88 1807 288 09 27307 4384 89 1794 320 0a 24576 4416 8a 1781 352 0b 22342 4448 8b 1768 384 0c 20480 4480 8c 1755 416 0d 18905 4512 8d 1743 448 0e 17554 4544 8e 1731 480 0f 16384 4576 8f 1719 512 10 15360 4608 90 1707 544 11 14456 4640 91 1695 576 12 13653 4672 92 1683 608 13 12935 4704 93 1672 640 14 12288 4736 94 1661 672 15 11703 4768 95 1649 704 16 11171 4800 96 1638 736 17 10685 4832 97 1628 768 18 10240 4864 98 1617
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 81 revision 0.85 (01-29-08) datasheet 800 19 9830 4896 99 1606 832 1a 9452 4928 9a 1596 864 1b 9102 4960 9b 1586 896 1c 8777 4992 9c 1575 928 1d 8474 5024 9d 1565 960 1e 8192 5056 9e 1555 992 1f 7928 5088 9f 1546 1024 20 7680 5120 a0 1536 1056 21 7447 5152 a1 1526 1088 22 7228 5184 a2 1517 1120 23 7022 5216 a3 1508 1152 24 6827 5248 a4 1499 1184 25 6642 5280 a5 1489 1216 26 6467 5312 a6 1480 1248 27 6302 5344 a7 1472 1280 28 6144 5376 a8 1463 1312 29 5994 5408 a9 1454 1344 2a 5851 5440 aa 1446 1376 2b 5715 5472 ab 1437 1408 2c 5585 5504 ac 1429 1440 2d 5461 5536 ad 1421 1472 2e 5343 5568 ae 1412 1504 2f 5229 5600 af 1404 1536 30 5120 5632 b0 1396 1568 31 5016 5664 b1 1388 1600 32 4915 5696 b2 1381 1632 33 4819 5728 b3 1373 1664 34 4726 5760 b4 1365 1696 35 4637 5792 b5 1358 1728 36 4551 5824 b6 1350 1760 37 4468 5856 b7 1343 1792 38 4389 5888 b8 1336 table b.1 tachometer count to rpm look up table (range = 1000 rpm) (continued) tach count (decimal) register reading (hex) fan speed (rpm) tach count (decimal) register reading (hex) fan speed (rpm)
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 82 smsc emc2103 datasheet 1824 39 4312 5920 b9 1328 1856 3a 4237 5952 ba 1321 1888 3b 4165 5984 bb 1314 1920 3c 4096 6016 bc 1307 1952 3d 4029 6048 bd 1300 1984 3e 3964 6080 be 1293 2016 3f 3901 6112 bf 1287 2048 40 3840 6144 c0 1280 2080 41 3781 6176 c1 1273 2112 42 3724 6208 c2 1267 2144 43 3668 6240 c3 1260 2176 44 3614 6272 c4 1254 2208 45 3562 6304 c5 1248 2240 46 3511 6336 c6 1241 2272 47 3461 6368 c7 1235 2304 48 3413 6400 c8 1229 2336 49 3367 6432 c9 1223 2368 4a 3321 6464 ca 1217 2400 4b 3277 6496 cb 1211 2432 4c 3234 6528 cc 1205 2464 4d 3192 6560 cd 1199 2496 4e 3151 6592 ce 1193 2528 4f 3111 6624 cf 1187 2560 50 3072 6656 d0 1182 2592 51 3034 6688 d1 1176 2624 52 2997 6720 d2 1170 2656 53 2961 6752 d3 1165 2688 54 2926 6784 d4 1159 2720 55 2891 6816 d5 1154 2752 56 2858 6848 d6 1148 2784 57 2825 6880 d7 1143 table b.1 tachometer count to rpm look up table (range = 1000 rpm) (continued) tach count (decimal) register reading (hex) fan speed (rpm) tach count (decimal) register reading (hex) fan speed (rpm)
rpm-based fan controller with hw thermal shutdown datasheet smsc emc2103 83 revision 0.85 (01-29-08) datasheet 2816 58 2793 6912 d8 1138 2848 59 2761 6944 d9 1133 2880 5a 2731 6976 da 1127 2912 5b 2701 7008 db 1122 2944 5c 2671 7040 dc 1117 2976 5d 2643 7072 dd 1112 3008 5e 2614 7104 de 1107 3040 5f 2587 7136 df 1102 3072 60 2560 7168 e0 1097 3104 61 2534 7200 e1 1092 3136 62 2508 7232 e2 1087 3168 63 2482 7264 e3 1083 3200 64 2458 7296 e4 1078 3232 65 2433 7328 e5 1073 3264 66 2409 7360 e6 1069 3296 67 2386 7392 e7 1064 3328 68 2363 7424 e8 1059 3360 69 2341 7456 e9 1055 3392 6a 2318 7488 ea 1050 3424 6b 2297 7520 eb 1046 3456 6c 2276 7552 ec 1041 3488 6d 2255 7584 ed 1037 3520 6e 2234 7616 ee 1033 3552 6f 2214 7648 ef 1028 3584 70 2194 7680 f0 1024 3616 71 2175 7712 f1 1020 3648 72 2156 7744 f2 1016 3680 73 2137 7776 f3 1011 3712 74 2119 7808 f4 1007 3744 75 2101 7840 f5 1003 3776 76 2083 7872 f6 999 3808 77 2065 7904 f7 995 table b.1 tachometer count to rpm look up table (range = 1000 rpm) (continued) tach count (decimal) register reading (hex) fan speed (rpm) tach count (decimal) register reading (hex) fan speed (rpm)
rpm-based fan controller with hw thermal shutdown datasheet revision 0.85 (01-29-08) 84 smsc emc2103 datasheet 3840 78 2048 7936 f8 991 3872 79 2031 7968 f9 987 3904 7a 2014 8000 fa 983 3936 7b 1998 8032 fb 979 3968 7c 1982 8064 fc 975 4000 7d 1966 8096 fd 971 4032 7e 1950 8128 fe 968 4064 7f 1935 8160 ff 964 table b.1 tachometer count to rpm look up table (range = 1000 rpm) (continued) tach count (decimal) register reading (hex) fan speed (rpm) tach count (decimal) register reading (hex) fan speed (rpm)

▲Up To Search▲

Price & Availability of STANDARDMICROSYSTEMSCORP-EMC2103-3-KP

	To Download STANDARDMICROSYSTEMSCORP-EMC2103-3-KP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .